def add_decode_cern_be_vme(root, module, isigs):
"Generate internal signals used by decoder/processes from CERN-BE-VME bus."
isigs.rd_int = root.h_bus['rd']
isigs.wr_int = root.h_bus['wr']
isigs.rd_ack = HDLSignal('rd_ack_int') # Ack for read
isigs.wr_ack = HDLSignal('wr_ack_int') # Ack for write
module.decls.extend([isigs.rd_ack, isigs.wr_ack])
module.stmts.append(HDLAssign(root.h_bus['rack'], isigs.rd_ack))
module.stmts.append(HDLAssign(root.h_bus['wack'], isigs.wr_ack))
def gen_bus_slave(root, module, prefix, n, interface, busgroup):
if interface == 'wb-32-be':
n.h_bus = gen_bus_slave_wb32(root, module, module, n.name,
n.description, busgroup)
# Internal signals
n.h_wr = HDLSignal(prefix + 'wr')
module.decls.append(n.h_wr)
n.h_rd = HDLSignal(prefix + 'rd')
module.decls.append(n.h_rd)
elif interface == 'sram':
n.h_bus = {}
gen_bus_slave_sram(root, prefix, n)
else:
raise AssertionError(interface)
def add_ports_reg(root, module, n):
for f in n.children:
w = None if f.c_iowidth == 1 else f.c_iowidth
# Input
if f.hdl_type == 'wire' and n.access in ['ro', 'rw']:
f.h_iport = add_module_port(root, module, f.c_name, w, dir='IN')
f.h_iport.comment = f.description
else:
f.h_iport = None
# Output
if n.access in ['wo', 'rw']:
f.h_oport = add_module_port(root, module, f.c_name, w, dir='OUT')
f.h_oport.comment = f.description
else:
f.h_oport = None
# Write strobe
if f.hdl_write_strobe:
f.h_wport = add_module_port(root,
module,
f.c_name + '_wr',
None,
dir='OUT')
else:
f.h_wport = None
# Register
if f.hdl_type == 'reg':
f.h_reg = HDLSignal(f.c_name + '_reg', w)
module.decls.append(f.h_reg)
else:
f.h_reg = None
def generate_hdl(root):
isigs = Isigs()
root.h_max_delay = compute_max_delay(root)
module = gen_hdl_header(root, isigs)
# Add ports
iogroup = root.get_extension('x_hdl', 'iogroup')
if iogroup is not None:
root.h_itf = HDLInterface('t_' + iogroup)
module.global_decls.append(root.h_itf)
grp = module.add_port_group(iogroup, root.h_itf, True)
grp.comment = 'Wires and registers'
root.h_ports = grp
else:
root.h_itf = None
root.h_ports = module
add_ports(root, module, root)
module.stmts.append(HDLComment('Assign outputs'))
root.h_ram = None
root.h_ram_wr_dly = None
wire_regs(root, module, isigs, root)
module.stmts.append(HDLComment('Process for write requests.'))
add_write_process(root, module, isigs)
if root.h_max_delay >= 1:
root.h_reg_rdat_int = HDLSignal('reg_rdat_int', root.c_word_bits)
module.decls.append(root.h_reg_rdat_int)
root.h_rd_ack1_int = HDLSignal('rd_ack1_int')
module.decls.append(root.h_rd_ack1_int)
module.stmts.append(HDLComment('Process for registers read.'))
add_read_reg_process(root, module, isigs)
module.stmts.append(HDLComment('Process for read requests.'))
add_read_process(root, module, isigs)
return module
def add_decode_wb(root, module, isigs):
"Generate internal signals used by decoder/processes from WB bus."
isigs.rd_int = HDLSignal('rd_int') # Read access
isigs.wr_int = HDLSignal('wr_int') # Write access
isigs.rd_ack = HDLSignal('rd_ack_int') # Ack for read
isigs.wr_ack = HDLSignal('wr_ack_int') # Ack for write
# Internal signals for wb.
isigs.wb_en = HDLSignal('wb_en')
isigs.ack_int = HDLSignal('ack_int') # Ack
module.decls.extend([
isigs.wb_en, isigs.rd_int, isigs.wr_int, isigs.ack_int, isigs.rd_ack,
isigs.wr_ack
])
module.stmts.append(
HDLAssign(isigs.wb_en, HDLAnd(root.h_bus['cyc'], root.h_bus['stb'])))
module.stmts.append(
HDLAssign(isigs.rd_int, HDLAnd(isigs.wb_en, HDLNot(root.h_bus['we']))))
module.stmts.append(
HDLAssign(isigs.wr_int, HDLAnd(isigs.wb_en, root.h_bus['we'])))
module.stmts.append(
HDLAssign(isigs.ack_int, HDLOr(isigs.rd_ack, isigs.wr_ack)))
module.stmts.append(HDLAssign(root.h_bus['ack'], isigs.ack_int))
module.stmts.append(
HDLAssign(root.h_bus['stall'],
HDLAnd(HDLNot(isigs.ack_int), isigs.wb_en)))
def wire_array_reg(root, module, reg):
if root.h_ram is None:
module.deps.append(('work', 'wbgen2_pkg'))
root.h_ram = True
root.h_ram_wr_dly = HDLSignal("wr_dly_int")
module.decls.append(root.h_ram_wr_dly)
inst = HDLInstance(reg.name + "_raminst", "wbgen2_dpssram")
module.stmts.append(inst)
inst.params.append(("g_data_width", HDLNumber(reg.c_rwidth)))
inst.params.append(("g_size", HDLNumber(1 << reg.h_addr_width)))
inst.params.append(("g_addr_width", HDLNumber(reg.h_addr_width)))
inst.params.append(("g_dual_clock", HDLBool(False)))
inst.params.append(("g_use_bwsel", HDLBool(False)))
inst.conns.append(("clk_a_i", root.h_bus['clk']))
inst.conns.append(("clk_b_i", root.h_bus['clk']))
inst.conns.append(
("addr_a_i", HDLSlice(root.h_bus['adr'], 0, reg.h_addr_width)))
inst.conns.append(("addr_b_i", reg.h_addr))
nbr_bytes = reg.c_rwidth // tree.BYTE_SIZE
reg.h_sig_bwsel = HDLSignal(reg.name + '_int_bwsel', nbr_bytes)
module.decls.append(reg.h_sig_bwsel)
inst.conns.append(("bwsel_b_i", reg.h_sig_bwsel))
inst.conns.append(("bwsel_a_i", reg.h_sig_bwsel))
if reg.access == 'ro':
raise AssertionError # TODO
inst.conns.append(("data_a_o", reg.h_dat))
inst.conns.append(("rd_a_i", rd_sig))
else:
# External port is RO.
reg.h_sig_dato = HDLSignal(reg.name + '_int_dato', reg.c_rwidth)
module.decls.append(reg.h_sig_dato)
reg.h_dat_ign = HDLSignal(reg.name + '_ext_dat', reg.c_rwidth)
module.decls.append(reg.h_dat_ign)
reg.h_sig_rd = HDLSignal(reg.name + '_int_rd')
module.decls.append(reg.h_sig_rd)
reg.h_sig_wr = HDLSignal(reg.name + '_int_wr')
module.decls.append(reg.h_sig_wr)
reg.h_ext_wr = HDLSignal(reg.name + '_ext_wr')
module.decls.append(reg.h_ext_wr)
module.stmts.append(HDLAssign(reg.h_ext_wr, bit_0))
inst.conns.append(("data_a_i", root.h_bus['dati']))
inst.conns.append(("data_a_o", reg.h_sig_dato))
inst.conns.append(("rd_a_i", reg.h_sig_rd))
inst.conns.append(("wr_a_i", reg.h_sig_wr))
inst.conns.append(("data_b_i", reg.h_dat_ign))
inst.conns.append(("data_b_o", reg.h_dat))
inst.conns.append(("rd_b_i", reg.h_rd))
inst.conns.append(("wr_b_i", reg.h_ext_wr))
module.stmts.append(
HDLAssign(reg.h_sig_bwsel, HDLReplicate(bit_1, nbr_bytes)))
def gen_gena_regctrl(root):
module = gen_hdl.gen_hdl_header(root)
module.name = 'RegCtrl_{}'.format(root.name)
module.libraries.append('CommonVisual')
lib = get_gena_gen(root, 'vhdl-library', 'work')
module.deps.append((lib, 'MemMap_{}'.format(root.name)))
isigs = gen_hdl.Isigs()
isigs.Loc_VMERdMem = HDLSignal('Loc_VMERdMem', 3)
isigs.Loc_VMEWrMem = HDLSignal('Loc_VMEWrMem', 2)
module.decls.extend([isigs.Loc_VMERdMem, isigs.Loc_VMEWrMem])
root.h_has_rmw = False
root.h_has_creg = False
root.h_has_srff = False
gen_hdl_area_decls(root, '', root, module, isigs)
gen_hdl_area(root, '', root, root, module, isigs)
gen_hdl_strobeseq(root, module, isigs)
gen_hdl_misc_root(root, module, isigs)
gen_hdl_components(root, module)
return module
def gen_hdl_reg_decls(reg, pfx, root, module, isigs):
# Generate ports
mode = 'OUT' if reg.access in WRITE_ACCESS else 'IN'
mux = get_gena_gen(reg, 'mux', None)
# FIXME: should it be an error ?
reg.h_has_mux = mux != None and not get_gena_gen(reg, 'ext-creg', False)
if mux:
mux = extract_mux(root, mux, reg)
else:
mux = Mux()
mux.codelist = [('', 0)]
reg.h_mux = mux
reg.h_port = None
if get_gena_gen(reg, 'no-split'):
reg.h_port = []
for suff, _ in reg.h_mux.codelist:
port = HDLPort(pfx + reg.name + suff, size=reg.c_iowidth, dir=mode)
module.ports.append(port)
reg.h_port.append(port)
elif get_gena_gen(reg, 'ext-creg'):
if reg.access in READ_ACCESS:
reg.h_port = HDLPort(pfx + reg.name, size=reg.c_rwidth, dir='IN')
module.ports.append(reg.h_port)
if reg.access in WRITE_ACCESS:
reg.h_portsel = []
for i in reversed(range(reg.c_nwords)):
sig = HDLPort('{}{}_Sel{}'.format(pfx, reg.name,
subsuffix(i, reg.c_nwords)),
dir='OUT')
reg.h_portsel.insert(0, sig)
module.ports.append(sig)
else:
for f in reg.children:
sz, lo = (None, None) if f.hi is None else (f.c_iowidth, f.lo)
fname = ('_' + f.name) if f.name is not None else ''
f.h_port = []
for suff, _ in reg.h_mux.codelist:
port = HDLPort(pfx + reg.name + suff + fname,
size=sz,
lo_idx=lo,
dir=mode)
module.ports.append(port)
f.h_port.append(port)
reg.h_busout = None
if get_gena_gen(reg, 'bus-out'):
reg.h_busout = HDLPort(pfx + reg.name, size=reg.c_rwidth, dir='OUT')
module.ports.append(reg.h_busout)
if get_gena_gen(reg, 'ext-acm') and reg.access != 'ro':
reg.h_acm = HDLPort(pfx + reg.name + '_ACM', size=reg.c_rwidth)
module.ports.append(reg.h_acm)
else:
reg.h_acm = None
reg.h_wrstrobe = []
if get_gena_gen(reg, 'write-strobe') and reg.access in WRITE_ACCESS:
for i in reversed(range(reg.c_nwords)):
ports = []
for suff, _ in reg.h_mux.codelist:
port = HDLPort(pfx + reg.name + suff + '_WrStrobe' +
subsuffix(i, reg.c_nwords),
dir='OUT')
ports.append(port)
module.ports.append(port)
reg.h_wrstrobe.insert(0, ports)
reg.h_SRFF = None
reg.h_ClrSRFF = None
srff = get_gena_gen(reg, 'srff')
if srff:
reg.h_SRFF = HDLPort(pfx + reg.name + '_SRFF',
size=reg.c_rwidth,
dir='OUT')
module.ports.append(reg.h_SRFF)
reg.h_ClrSRFF = HDLPort(pfx + reg.name + '_ClrSRFF')
module.ports.append(reg.h_ClrSRFF)
reg.h_rdstrobe = []
if get_gena_gen(reg, 'read-strobe') and reg.access in READ_ACCESS:
for i in reversed(range(reg.c_nwords)):
port = HDLPort(pfx + reg.name + '_RdStrobe' +
subsuffix(i, reg.c_nwords),
dir='OUT')
reg.h_rdstrobe.insert(0, port)
module.ports.append(port)
# Create Loc_ signal
if get_gena_gen(reg, 'ext-creg') and reg.access == 'wo':
reg.h_loc = None
else:
reg.h_loc = HDLSignal('Loc_{}{}'.format(pfx, reg.name), reg.c_rwidth)
module.decls.append(reg.h_loc)
if reg.h_has_mux:
reg.h_loc_mux = []
for suff, _ in mux.codelist:
sig = HDLSignal('Loc_{}{}{}'.format(pfx, reg.name, suff),
reg.c_rwidth)
module.decls.append(sig)
reg.h_loc_mux.append(sig)
reg.h_regok = HDLSignal('RegOK_{}{}'.format(pfx, reg.name))
module.decls.append(reg.h_regok)
else:
reg.h_loc_mux = [reg.h_loc]
# Create Loc_x_SRFF
reg.h_loc_SRFF = None
if srff:
reg.h_loc_SRFF = HDLSignal('Loc_{}{}_SRFF'.format(pfx, reg.name),
reg.c_rwidth)
module.decls.append(reg.h_loc_SRFF)
# Create RdSel_ signals
reg.h_rdsel = []
if reg.h_rdstrobe:
for i in reversed(range(reg.c_nwords)):
sig = HDLSignal('RdSel_{}{}{}'.format(pfx, reg.name,
subsuffix(i, reg.c_nwords)))
reg.h_rdsel.insert(0, sig)
module.decls.append(sig)
# Create WrSel_ signals
reg.h_wrsel = []
reg.h_wrsel_mux = []
if reg.access in WRITE_ACCESS:
for i in reversed(range(reg.c_nwords)):
sig = HDLSignal('WrSel_{}{}{}'.format(pfx, reg.name,
subsuffix(i, reg.c_nwords)))
module.decls.append(sig)
reg.h_wrsel.insert(0, sig)
if reg.h_has_mux:
sels = []
for suff, _ in reg.h_mux.codelist:
sig = HDLSignal('WrSel_{}{}{}{}'.format(
pfx, reg.name, suff, subsuffix(i, reg.c_nwords)))
sels.append(sig)
module.decls.append(sig)
reg.h_wrsel_mux.insert(0, sels)
else:
reg.h_wrsel_mux.insert(0, [reg.h_wrsel[0]])
def gen_hdl_ext_bus(n, bwidth, acc, pfx, root, module):
# Generate ports
dwidth = min(bwidth, root.c_word_bits)
adr_sz = ilog2(n.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
if not root.h_bussplit:
n.h_sel = HDLPort('{}{}_Sel'.format(pfx, n.name), dir='OUT')
n.h_addr = HDLPort('{}{}_Addr'.format(pfx, n.name),
size=adr_sz,
lo_idx=adr_lo,
dir='OUT')
module.ports.extend([n.h_sel, n.h_addr])
# Sel_ signal
n.h_sel_sig = HDLSignal('Sel_{}{}'.format(pfx, n.name))
module.decls.append(n.h_sel_sig)
n.h_rdsel_sig, n.h_wrsel_sig = n.h_sel_sig, n.h_sel_sig
if acc in READ_ACCESS:
if root.h_bussplit:
n.h_rdsel = HDLPort('{}{}_RdSel'.format(pfx, n.name), dir='OUT')
n.h_rdaddr = HDLPort('{}{}_RdAddr'.format(pfx, n.name),
size=adr_sz,
lo_idx=adr_lo,
dir='OUT')
module.ports.extend([n.h_rdsel, n.h_rdaddr])
n.h_rdsel_sig = HDLSignal('RdSel_{}{}'.format(pfx, n.name))
module.decls.append(n.h_rdsel_sig)
else:
n.h_rdsel = n.h_sel
n.h_rdaddr = n.h_addr
n.h_rdsel_sig = n.h_sel_sig
n.h_rddata = HDLPort('{}{}_RdData'.format(pfx, n.name), size=dwidth)
module.ports.append(n.h_rddata)
if acc in WRITE_ACCESS:
if root.h_bussplit:
n.h_wrsel = HDLPort('{}{}_WrSel'.format(pfx, n.name), dir='OUT')
n.h_wraddr = HDLPort('{}{}_WrAddr'.format(pfx, n.name),
size=adr_sz,
lo_idx=adr_lo,
dir='OUT')
module.ports.extend([n.h_wrsel, n.h_wraddr])
n.h_wrsel_sig = HDLSignal('WrSel_{}{}'.format(pfx, n.name))
module.decls.append(n.h_wrsel_sig)
else:
n.h_wrsel = n.h_sel
n.h_wraddr = n.h_addr
n.h_wrsel_sig = n.h_sel_sig
n.h_wrdata = HDLPort('{}{}_WrData'.format(pfx, n.name),
size=dwidth,
dir='OUT')
module.ports.append(n.h_wrdata)
if acc in READ_ACCESS:
n.h_rdmem = HDLPort('{}{}_RdMem'.format(pfx, n.name), dir='OUT')
module.ports.append(n.h_rdmem)
if acc in WRITE_ACCESS:
n.h_wrmem = HDLPort('{}{}_WrMem'.format(pfx, n.name), dir='OUT')
module.ports.append(n.h_wrmem)
if acc in READ_ACCESS:
n.h_rddone = HDLPort('{}{}_RdDone'.format(pfx, n.name))
module.ports.append(n.h_rddone)
if acc in WRITE_ACCESS:
n.h_wrdone = HDLPort('{}{}_WrDone'.format(pfx, n.name))
module.ports.append(n.h_wrdone)
if acc in READ_ACCESS and root.c_buserr:
n.h_rderror = HDLPort('{}{}_RdError'.format(pfx, n.name),
default=bit_0)
module.ports.append(n.h_rderror)
if acc in WRITE_ACCESS and root.c_buserr:
n.h_wrerror = HDLPort('{}{}_WrError'.format(pfx, n.name),
default=bit_0)
module.ports.append(n.h_wrerror)
def gen_hdl_area_decls(area, pfx, root, module, isigs):
area.h_isigs = isigs
sigs = [('{}CRegRdData', root.c_word_bits), ('{}CRegRdOK', None),
('{}CRegWrOK', None), ('Loc_{}CRegRdData', root.c_word_bits),
('Loc_{}CRegRdOK', None), ('Loc_{}CRegWrOK', None),
('{}RegRdDone', None), ('{}RegWrDone', None),
('{}RegRdData', root.c_word_bits), ('{}RegRdOK', None),
('Loc_{}RegRdData', root.c_word_bits), ('Loc_{}RegRdOK', None),
('{}MemRdData', root.c_word_bits), ('{}MemRdDone', None),
('{}MemWrDone', None), ('Loc_{}MemRdData', root.c_word_bits),
('Loc_{}MemRdDone', None), ('Loc_{}MemWrDone', None),
('{}RdData', root.c_word_bits), ('{}RdDone', None),
('{}WrDone', None)]
if root.c_buserr:
sigs.extend([
('{}RegRdError', None),
('{}RegWrError', None),
('{}MemRdError', None),
('{}MemWrError', None),
('Loc_{}MemRdError', None),
('Loc_{}MemWrError', None),
('{}RdError', None),
('{}WrError', None),
])
for tpl, size in sigs:
name = tpl.format(pfx)
s = HDLSignal(name, size)
setattr(isigs, tpl.format(''), s)
module.decls.append(s)
for el in area.children:
el.h_ignored = False
if isinstance(el, tree.Reg):
if get_gena_gen(el, 'ignore'):
el.h_ignored = True
else:
gen_hdl_reg_decls(el, pfx, root, module, isigs)
elif isinstance(el, tree.Array):
gen_hdl_mem_decls(el, pfx, root, module, isigs)
elif isinstance(el, (tree.Block, tree.Submap)):
if el.get_extension('x_gena', 'reserved', False):
# Discard
el.h_ignored = True
continue
if isinstance(el, tree.Submap):
include = get_gena_gen(el, 'include', None)
elif get_gena_gen(el, 'ext-area', False):
include = 'external'
else:
# A regular area.
include = True
if include is not None:
el.h_has_external = (include == 'external')
el_isigs = gen_hdl.Isigs()
npfx = pfx + el.name + '_'
if el.h_has_external:
gen_hdl_ext_bus(el, root.c_word_size * tree.BYTE_SIZE,
'rw', pfx, root, module)
el_isigs.RdData = el.h_rddata
el_isigs.RdDone = el.h_rddone
el_isigs.WrDone = el.h_wrdone
if root.c_buserr:
el_isigs.RdError = el.h_rderror
el_isigs.WrError = el.h_wrerror
el.h_isigs = el_isigs
else:
if isinstance(el, tree.Submap):
assert len(el.children) == 0
assert get_gena_gen(el, 'include') == 'internal'
el.children = el.c_submap.children
lib = get_gena_gen(el.c_submap, 'vhdl-library')
if not lib:
lib = 'work'
pkg = (lib, 'MemMap_{}'.format(el.c_submap.name))
if pkg not in module.deps:
module.deps.append(pkg)
gen_hdl_area_decls(el, npfx, root, module, el_isigs)
else:
el.h_ignored = True
else:
raise AssertionError