Beispiel #1
0
    def _write_config_files(self):
        #Future improvement: Separate include directories of c and verilog files
        incdirs = set()
        src_files = []

        (src_files, incdirs) = self._get_fileset_files(['synth', 'verilator'])

        self.verilator_file = self.system.sanitized_name + '.vc'

        with open(os.path.join(self.work_root, self.verilator_file), 'w') as f:
            f.write('--Mdir .\n')
            if self.system.verilator.source_type == 'systemC':
                f.write('--sc\n')
            else:
                f.write('--cc\n')

            for core in self.cores:
                if core.verilator:
                    for lib in core.verilator.libs:
                        f.write('-LDFLAGS {}\n'.format(lib))
            for include_dir in incdirs:
                f.write("+incdir+" + include_dir + '\n')
                f.write("-CFLAGS -I{}\n".format(include_dir))
            opt_c_files = []
            for src_file in src_files:
                if src_file.file_type.startswith(
                        "systemVerilogSource"
                ) or src_file.file_type.startswith("verilogSource"):
                    f.write(src_file.name + '\n')
                elif src_file.file_type in [
                        'cppSource', 'systemCSource', 'cSource'
                ]:
                    opt_c_files.append(src_file.name)
            f.write('--top-module {}\n'.format(self.top_module))
            f.write('--exe\n')
            f.write('\n'.join(opt_c_files))
            f.write('\n')

        with open(os.path.join(self.work_root, 'Makefile'), 'w') as makefile:
            makefile.write(MAKEFILE_TEMPLATE)

        with open(os.path.join(self.work_root, 'config.mk'), 'w') as config_mk:
            config_mk.write(
                CONFIG_MK_TEMPLATE.format(
                    top_module=self.top_module,
                    vc_file=self.verilator_file,
                    verilator_options=' '.join(
                        self.system.verilator.verilator_options)))

        #convert verilog defines into C file
        for f in self.system.verilator.define_files:
            read_file = os.path.join(self._basepath(self.system), f)
            write_file = os.path.splitext(read_file) + '.h'
            utils.convert_V2H(read_file, write_file)
Beispiel #2
0
    def _write_config_files(self):
        self.verilator_file = 'input.vc'
        f = open(os.path.join(self.sim_root,self.verilator_file),'w')

        for include_dir in self.verilog.include_dirs:
            f.write("+incdir+" + os.path.abspath(include_dir) + '\n')
        for src_file in self.verilog.src_files:
            f.write(os.path.abspath(src_file) + '\n')
        f.close()
        #convert verilog defines into C file
        for files in self.define_files:
            read_file = os.path.join(self.src_root,files)
            write_file = os.path.join(os.path.dirname(os.path.join(self.sim_root,self.tb_toplevel)),os.path.splitext(os.path.basename(files))[0]+'.h')
            utils.convert_V2H(read_file, write_file)
Beispiel #3
0
    def _write_config_files(self):
        self.verilator_file = 'input.vc'
        f = open(os.path.join(self.sim_root, self.verilator_file), 'w')

        for include_dir in self.verilog.include_dirs:
            f.write("+incdir+" + os.path.abspath(include_dir) + '\n')
        for src_file in self.verilog.src_files:
            f.write(os.path.abspath(src_file) + '\n')
        f.close()
        #convert verilog defines into C file
        for files in self.define_files:
            read_file = os.path.join(self.src_root, files)
            write_file = os.path.join(
                os.path.dirname(os.path.join(self.sim_root, self.tb_toplevel)),
                os.path.splitext(os.path.basename(files))[0] + '.h')
            utils.convert_V2H(read_file, write_file)
Beispiel #4
0
    def _write_config_files(self):
        self.verilator_file = 'input.vc'
        f = open(os.path.join(self.work_root,self.verilator_file),'w')

        incdirs = set()
        src_files = []

        (src_files, incdirs) = self._get_fileset_files(['synth', 'verilator'])
        for include_dir in incdirs:
            f.write("+incdir+" + include_dir + '\n')
        for src_file in src_files:
            f.write(src_file.name + '\n')
        f.close()
        #convert verilog defines into C file
        for files in self.define_files:
            read_file = os.path.join(self.src_root,files)
            write_file = os.path.join(os.path.dirname(os.path.join(self.work_root,self.tb_toplevel)),os.path.splitext(os.path.basename(files))[0]+'.h')
            utils.convert_V2H(read_file, write_file)
    def _write_config_files(self):
        self.verilator_file = 'input.vc'
        f = open(os.path.join(self.sim_root,self.verilator_file),'w')

        incdirs = set()
        src_files = []

        (src_files, incdirs) = self._get_fileset_files(['synth', 'verilator'])
        for include_dir in incdirs:
            f.write("+incdir+" + include_dir + '\n')
        for src_file in src_files:
            f.write(src_file.name + '\n')
        f.close()
        #convert verilog defines into C file
        for files in self.define_files:
            read_file = os.path.join(self.src_root,files)
            write_file = os.path.join(os.path.dirname(os.path.join(self.sim_root,self.tb_toplevel)),os.path.splitext(os.path.basename(files))[0]+'.h')
            utils.convert_V2H(read_file, write_file)