def test_execute_sw(self):
# sw $t6, $a0, 0 (0 is the offset amount)
this_register_file = list(PipelineInterfaceTest.register_file)
this_instruction_list = list(
PipelineInterfaceTest.Instruction_list)[10:]
this_memory_file = PipelineInterfaceTest.data_memory.copy()
this_register_file[decode_asm_register(
'a0')] = create_sized_binary_num(4, 32)
this_register_file[decode_asm_register(
't6')] = create_sized_binary_num(1995, 32)
interface = PipelineInterface(this_instruction_list,
PipelineInterfaceTest.starting_address,
this_register_file, this_memory_file)
interface.trigger_clock_cycle()
self.assertEqual(
create_sized_binary_num(1995, 32),
interface.retrieve_data_memory()[create_sized_binary_num(4, 32)])
def test_execute_slt_not_set(self):
# slt $t1, $t0, $t4
this_register_file = list(PipelineInterfaceTest.register_file)
this_instruction_list = list(
PipelineInterfaceTest.Instruction_list)[6:]
this_memory_file = PipelineInterfaceTest.data_memory.copy()
this_register_file[decode_asm_register(
't0')] = create_sized_binary_num(22, 32)
this_register_file[decode_asm_register(
't4')] = create_sized_binary_num(4, 32)
interface = PipelineInterface(this_instruction_list,
PipelineInterfaceTest.starting_address,
this_register_file, this_memory_file)
interface.trigger_clock_cycle()
self.assertEqual(
create_sized_binary_num(0, 32),
interface.retrieve_register_list()[decode_asm_register('t1')])
def test_execute_sub(self):
this_register_file = list(PipelineInterfaceTest.register_file)
this_instruction_list = list(
PipelineInterfaceTest.Instruction_list)[4:]
this_register_file[decode_asm_register(
'a1')] = create_sized_binary_num(
24, 32) # put something in register $t2
this_register_file[decode_asm_register(
't8')] = create_sized_binary_num(
18, 32) # put something in register $t3
interface = PipelineInterface(this_instruction_list,
PipelineInterfaceTest.starting_address,
this_register_file,
PipelineInterfaceTest.data_memory)
interface.trigger_clock_cycle()
self.assertEqual(
create_sized_binary_num(24 - 18, 32),
interface.retrieve_register_list()[decode_asm_register('a1')])
def test_execute_mult(self):
# mult $s2, $s1, $t3
this_register_file = list(PipelineInterfaceTest.register_file)
this_instruction_list = list(
PipelineInterfaceTest.Instruction_list)[12:]
this_register_file[decode_asm_register(
's1')] = create_sized_binary_num(
54, 32) # put something in register $t2
this_register_file[decode_asm_register(
't3')] = create_sized_binary_num(
2000, 32) # put something in register $t3
interface = PipelineInterface(this_instruction_list,
PipelineInterfaceTest.starting_address,
this_register_file,
PipelineInterfaceTest.data_memory)
interface.trigger_clock_cycle()
self.assertEqual(
create_sized_binary_num(54 * 2000, 32),
interface.retrieve_register_list()[decode_asm_register('s2')])
def test_execute_addi_instruction_2(self):
this_register_file = list(PipelineInterfaceTest.register_file)
this_instruction_list = list(
PipelineInterfaceTest.Instruction_list)[2:]
interface = PipelineInterface(this_instruction_list,
PipelineInterfaceTest.starting_address,
this_register_file,
PipelineInterfaceTest.data_memory)
interface.trigger_clock_cycle()
self.assertEqual(
create_sized_binary_num(257, 32),
interface.retrieve_register_list()[decode_asm_register('t4')])
def test_execute_beq_do_branch(self):
this_register_file = list(PipelineInterfaceTest.register_file)
this_register_file[decode_asm_register(
'a1')] = create_sized_binary_num(0, 32)
this_instruction_list = list(
PipelineInterfaceTest.Instruction_list)[3:]
interface = PipelineInterface(this_instruction_list,
PipelineInterfaceTest.starting_address,
this_register_file,
PipelineInterfaceTest.data_memory)
interface.trigger_clock_cycle()
expected_address = int(
PipelineInterfaceTest.var_exit
) * 4 + 4 # branch addresses are multiplied by 4 and relative to pc + 4
self.assertEqual(expected_address,
interface.retrieve_current_pc_address())
print(
"This program will execute the provided test program for my Pipeline Simulator."
)
print(
"Currently, the pipeline is single-cycle, with no hazard detection, forwaring, or pipelining"
)
print("Created by Trey Franklin")
print(
"-----------------------------------------------------------------------")
sleep(2)
print("Creating register file..")
register_file = [create_sized_binary_num(0, 32)
for i in range(0, 32)] # initialize all registers to zero
register_file[decode_asm_register('v0')] = create_sized_binary_num(0x0040, 32)
register_file[decode_asm_register('v1')] = create_sized_binary_num(0x1010, 32)
register_file[decode_asm_register('s2')] = create_sized_binary_num(0x000F, 32)
register_file[decode_asm_register('s3')] = create_sized_binary_num(0x00F0, 32)
register_file[decode_asm_register('t0')] = create_sized_binary_num(0x0000, 32)
register_file[decode_asm_register('a0')] = create_sized_binary_num(0x0010, 32)
register_file[decode_asm_register('a1')] = create_sized_binary_num(0x0005, 32)
print("Creating data memory..")
data_memory_addresses = [
create_sized_binary_num(i, 32) for i in range(0, 512, 4)
] # word addressing (increment by 4)
data_memory = {}
for i in data_memory_addresses:
data_memory[i] = create_sized_binary_num(
0, 32) # initialize valid memory addresses to zero