Ejemplo n.º 1
0
def get_add_symbol(s_new_lit):
    assert counter_and_u_new_lits or counter_latch_u_new_lits, \
        'not initialized'

    u_new_lit = strip_lit(s_new_lit)

    if u_new_lit == 0:
        input_, latch_, and_ = get_lit_type(u_new_lit)
        return input_ or latch_ or and_

    if u_new_lit in symbol_by_ulit:
        input_, latch_, and_ = get_lit_type(u_new_lit)
        return input_ or latch_ or and_

    if u_new_lit in [
            strip_lit(get_new_s_lit(reset)),
            strip_lit(get_new_s_lit(inc))
    ]:
        # previously input literal, it was not AND nor latch in the counter
        input_, latch_, and_ = get_lit_type(u_new_lit)
        return input_ or latch_ or and_

    assert u_new_lit in counter_and_u_new_lits or \
        u_new_lit in counter_latch_u_new_lits, "%s\n%s\n%s" % (u_new_lit, counter_and_u_new_lits, counter_latch_u_new_lits)

    if u_new_lit in counter_and_u_new_lits:
        aiglib.aiger_add_and(spec, u_new_lit, 1, 1)
    else:  # u_new_lit in counter_latch_u_new_lits:
        aiglib.aiger_add_latch(spec, u_new_lit, 1, 'counter_latch')

    symbol_by_ulit.add(u_new_lit)
    input_, latch_, and_ = get_lit_type(u_new_lit)
    return input_ or latch_ or and_
Ejemplo n.º 2
0
def get_add_symbol(s_new_lit):
    assert counter_and_u_new_lits or counter_latch_u_new_lits, \
        'not initialized'

    u_new_lit = strip_lit(s_new_lit)

    if u_new_lit == 0:
        input_, latch_, and_ = get_lit_type(u_new_lit)
        return input_ or latch_ or and_

    if u_new_lit in symbol_by_ulit:
        input_, latch_, and_ = get_lit_type(u_new_lit)
        return input_ or latch_ or and_

    if u_new_lit in [strip_lit(get_new_s_lit(reset)), strip_lit(get_new_s_lit(inc))]:
        # previously input literal, it was not AND nor latch in the counter
        input_, latch_, and_ = get_lit_type(u_new_lit)
        return input_ or latch_ or and_

    assert u_new_lit in counter_and_u_new_lits or \
        u_new_lit in counter_latch_u_new_lits, "%s\n%s\n%s" % (u_new_lit, counter_and_u_new_lits, counter_latch_u_new_lits)

    if u_new_lit in counter_and_u_new_lits:
        aiglib.aiger_add_and(spec, u_new_lit, 1, 1)
    else:  # u_new_lit in counter_latch_u_new_lits:
        aiglib.aiger_add_latch(spec, u_new_lit, 1, 'counter_latch')

    symbol_by_ulit.add(u_new_lit)
    input_, latch_, and_ = get_lit_type(u_new_lit)
    return input_ or latch_ or and_
Ejemplo n.º 3
0
def main(filename):
    #: :type: aiglib.aiger
    model = aiglib.aiger_init()
    aiglib.aiger_open_and_read_from_file(model, filename)

    if model.num_justice == 0:
        _write_result(model)
        return

    assert model.num_justice == 1
    assert model.justice.size == 1

    next_lit = (model.maxvar + 1) * 2

    # first, add all elements

    aiglib.aiger_add_input(model, next_lit, 'SYNT_2_HWMCC_aux')
    #: :type: aiglib.aiger_symbol
    aux = aiglib.aiger_is_input(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and1 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and2 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and3 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and4 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L1')
    #: :type: aiglib.aiger_and
    L1 = aiglib.aiger_is_latch(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L2')
    #: :type: aiglib.aiger_and
    L2 = aiglib.aiger_is_latch(model, next_lit)
    next_lit += 2

    #: :type: aiglib.aiger_symbol
    old_just_lit = aiglib.get_justice_lit(model, 0, 0)

    # second, define all connections
    and1.rhs0, and1.rhs1 = aux.lit + 1, L1.lit + 1
    and2.rhs0, and2.rhs1 = L1.lit, old_just_lit
    and3.rhs0, and3.rhs1 = and2.lhs + 1, L2.lit + 1
    and4.rhs0, and4.rhs1 = L2.lit + 1, L1.lit

    L1.next = and1.lhs + 1
    L2.next = and3.lhs + 1

    aiglib.set_justice_lit(model, 0, 0, and4.lhs)

    #
    _write_result(model)
Ejemplo n.º 4
0
def main(filename):
    #: :type: aiglib.aiger
    model = aiglib.aiger_init()
    aiglib.aiger_open_and_read_from_file(model, filename)

    if model.num_justice == 0:
        _write_result(model)
        return

    assert model.num_justice == 1
    assert model.justice.size == 1

    next_lit = (model.maxvar + 1) * 2

    # first, add all elements

    aiglib.aiger_add_input(model, next_lit, 'SYNT_2_HWMCC_aux')
    #: :type: aiglib.aiger_symbol
    aux = aiglib.aiger_is_input(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and1 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and2 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and3 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_and(model, next_lit, 1, 1)
    #: :type: aiglib.aiger_and
    and4 = aiglib.aiger_is_and(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L1')
    #: :type: aiglib.aiger_and
    L1 = aiglib.aiger_is_latch(model, next_lit)
    next_lit += 2

    aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L2')
    #: :type: aiglib.aiger_and
    L2 = aiglib.aiger_is_latch(model, next_lit)
    next_lit += 2

    #: :type: aiglib.aiger_symbol
    old_just_lit = aiglib.get_justice_lit(model, 0, 0)

    # second, define all connections
    and1.rhs0, and1.rhs1 = aux.lit + 1, L1.lit + 1
    and2.rhs0, and2.rhs1 = L1.lit, old_just_lit
    and3.rhs0, and3.rhs1 = and2.lhs + 1, L2.lit + 1
    and4.rhs0, and4.rhs1 = L2.lit + 1, L1.lit

    L1.next = and1.lhs + 1
    L2.next = and3.lhs + 1

    aiglib.set_justice_lit(model, 0, 0, and4.lhs)

    #
    _write_result(model)
Ejemplo n.º 5
0
 def add_gate(self, fresh_var, conjunct1, conjunct2):
     return aiger_add_and(self.spec, fresh_var, conjunct1, conjunct2)
Ejemplo n.º 6
0
 def add_gate(self, fresh_var, conjunct1, conjunct2):
     return aiger_add_and(self.spec, fresh_var, conjunct1, conjunct2)