def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
port0_axil_awaddr = Signal(intbv(0)[32:])
port0_axil_awprot = Signal(intbv(0)[3:])
port0_axil_awvalid = Signal(bool(False))
port0_axil_wdata = Signal(intbv(0)[32:])
port0_axil_wstrb = Signal(intbv(0)[4:])
port0_axil_wvalid = Signal(bool(False))
port0_axil_bready = Signal(bool(False))
port0_axil_araddr = Signal(intbv(0)[32:])
port0_axil_arprot = Signal(intbv(0)[3:])
port0_axil_arvalid = Signal(bool(False))
port0_axil_rready = Signal(bool(False))
# Outputs
port0_axil_awready = Signal(bool(False))
port0_axil_wready = Signal(bool(False))
port0_axil_bresp = Signal(intbv(0)[2:])
port0_axil_bvalid = Signal(bool(False))
port0_axil_arready = Signal(bool(False))
port0_axil_rdata = Signal(intbv(0)[32:])
port0_axil_rresp = Signal(intbv(0)[2:])
port0_axil_rvalid = Signal(bool(False))
# AXI4-Lite master
axil_master_inst = axil.AXILiteMaster()
axil_master_pause = Signal(bool(False))
axil_master_logic = axil_master_inst.create_logic(
clk,
rst,
m_axil_awaddr=port0_axil_awaddr,
m_axil_awprot=port0_axil_awprot,
m_axil_awvalid=port0_axil_awvalid,
m_axil_awready=port0_axil_awready,
m_axil_wdata=port0_axil_wdata,
m_axil_wstrb=port0_axil_wstrb,
m_axil_wvalid=port0_axil_wvalid,
m_axil_wready=port0_axil_wready,
m_axil_bresp=port0_axil_bresp,
m_axil_bvalid=port0_axil_bvalid,
m_axil_bready=port0_axil_bready,
m_axil_araddr=port0_axil_araddr,
m_axil_arprot=port0_axil_arprot,
m_axil_arvalid=port0_axil_arvalid,
m_axil_arready=port0_axil_arready,
m_axil_rdata=port0_axil_rdata,
m_axil_rresp=port0_axil_rresp,
m_axil_rvalid=port0_axil_rvalid,
m_axil_rready=port0_axil_rready,
pause=axil_master_pause,
name='master')
# AXI4-Lite RAM model
axil_ram_inst = axil.AXILiteRam(2**16)
axil_ram_pause = Signal(bool(False))
axil_ram_port0 = axil_ram_inst.create_port(
clk,
s_axil_awaddr=port0_axil_awaddr,
s_axil_awprot=port0_axil_awprot,
s_axil_awvalid=port0_axil_awvalid,
s_axil_awready=port0_axil_awready,
s_axil_wdata=port0_axil_wdata,
s_axil_wstrb=port0_axil_wstrb,
s_axil_wvalid=port0_axil_wvalid,
s_axil_wready=port0_axil_wready,
s_axil_bresp=port0_axil_bresp,
s_axil_bvalid=port0_axil_bvalid,
s_axil_bready=port0_axil_bready,
s_axil_araddr=port0_axil_araddr,
s_axil_arprot=port0_axil_arprot,
s_axil_arvalid=port0_axil_arvalid,
s_axil_arready=port0_axil_arready,
s_axil_rdata=port0_axil_rdata,
s_axil_rresp=port0_axil_rresp,
s_axil_rvalid=port0_axil_rvalid,
s_axil_rready=port0_axil_rready,
pause=axil_ram_pause,
latency=1,
name='port0')
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while not axil_master_inst.idle():
yield clk.posedge
def wait_pause_master():
while not axil_master_inst.idle():
axil_master_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axil_master_pause.next = False
yield clk.posedge
def wait_pause_slave():
while not axil_master_inst.idle():
axil_ram_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axil_ram_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: baseline")
current_test.next = 1
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
yield delay(100)
yield clk.posedge
print("test 2: direct write")
current_test.next = 2
axil_ram_inst.write_mem(0, b'test')
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(0, 4) == b'test'
yield delay(100)
yield clk.posedge
print("test 3: write via port0")
current_test.next = 3
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_master_inst.init_write(addr, test_data)
yield axil_master_inst.wait()
yield clk.posedge
data = axil_ram_inst.read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(addr, len(test_data)) == test_data
yield delay(100)
yield clk.posedge
print("test 4: read via port0")
current_test.next = 4
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_ram_inst.write_mem(addr, test_data)
axil_master_inst.init_read(addr, len(test_data))
yield axil_master_inst.wait()
yield clk.posedge
data = axil_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in range(1, 8):
for offset in range(4, 8):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d" % (length, offset))
addr = 256 * (16 * offset + length) + offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_ram_inst.write_mem(256 * (16 * offset + length),
b'\xAA' * 32)
axil_master_inst.init_write(addr, test_data)
yield wait()
yield clk.posedge
data = axil_ram_inst.read_mem(256 * (16 * offset + length),
32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(addr, length) == test_data
assert axil_ram_inst.read_mem(addr - 1, 1) == b'\xAA'
assert axil_ram_inst.read_mem(addr + length, 1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in range(1, 8):
for offset in range(4, 8):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d" % (length, offset))
addr = 256 * (16 * offset + length) + offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_master_inst.init_read(addr, length)
yield wait()
yield clk.posedge
data = axil_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 128
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32)
AXI_DATA_WIDTH = 32
AXI_ADDR_WIDTH = 64
AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8)
ENABLE_PARITY = 0
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_cq_tvalid = Signal(bool(0))
s_axis_cq_tlast = Signal(bool(0))
s_axis_cq_tuser = Signal(intbv(0)[85:])
m_axis_cc_tready = Signal(bool(0))
m_axil_awready = Signal(bool(0))
m_axil_wready = Signal(bool(0))
m_axil_bresp = Signal(intbv(0)[2:])
m_axil_bvalid = Signal(bool(0))
m_axil_arready = Signal(bool(0))
m_axil_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axil_rresp = Signal(intbv(0)[2:])
m_axil_rvalid = Signal(bool(0))
completer_id = Signal(intbv(0)[16:])
completer_id_enable = Signal(bool(0))
# Outputs
s_axis_cq_tready = Signal(bool(0))
m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_cc_tvalid = Signal(bool(0))
m_axis_cc_tlast = Signal(bool(0))
m_axis_cc_tuser = Signal(intbv(0)[33:])
m_axil_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axil_awprot = Signal(intbv(0)[3:])
m_axil_awvalid = Signal(bool(0))
m_axil_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axil_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:])
m_axil_wvalid = Signal(bool(0))
m_axil_bready = Signal(bool(0))
m_axil_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axil_arprot = Signal(intbv(2)[3:])
m_axil_arvalid = Signal(bool(0))
m_axil_rready = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
# sources and sinks
cq_source = axis_ep.AXIStreamSource()
cq_source_logic = cq_source.create_logic(clk,
rst,
tdata=s_axis_cq_tdata,
tkeep=s_axis_cq_tkeep,
tvalid=s_axis_cq_tvalid,
tready=s_axis_cq_tready,
tlast=s_axis_cq_tlast,
tuser=s_axis_cq_tuser,
name='cq_source')
cc_sink = axis_ep.AXIStreamSink()
cc_sink_logic = cc_sink.create_logic(clk,
rst,
tdata=m_axis_cc_tdata,
tkeep=m_axis_cc_tkeep,
tvalid=m_axis_cc_tvalid,
tready=m_axis_cc_tready,
tlast=m_axis_cc_tlast,
tuser=m_axis_cc_tuser,
name='cc_sink')
# AXI4-Lite RAM model
axil_ram_inst = axil.AXILiteRam(2**16)
axil_ram_port0 = axil_ram_inst.create_port(clk,
s_axil_awaddr=m_axil_awaddr,
s_axil_awprot=m_axil_awprot,
s_axil_awvalid=m_axil_awvalid,
s_axil_awready=m_axil_awready,
s_axil_wdata=m_axil_wdata,
s_axil_wstrb=m_axil_wstrb,
s_axil_wvalid=m_axil_wvalid,
s_axil_wready=m_axil_wready,
s_axil_bresp=m_axil_bresp,
s_axil_bvalid=m_axil_bvalid,
s_axil_bready=m_axil_bready,
s_axil_araddr=m_axil_araddr,
s_axil_arprot=m_axil_arprot,
s_axil_arvalid=m_axil_arvalid,
s_axil_arready=m_axil_arready,
s_axil_rdata=m_axil_rdata,
s_axil_rresp=m_axil_rresp,
s_axil_rvalid=m_axil_rvalid,
s_axil_rready=m_axil_rready,
latency=1,
name='ram')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_cq_tdata=s_axis_cq_tdata,
s_axis_cq_tkeep=s_axis_cq_tkeep,
s_axis_cq_tvalid=s_axis_cq_tvalid,
s_axis_cq_tready=s_axis_cq_tready,
s_axis_cq_tlast=s_axis_cq_tlast,
s_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cc_tdata=m_axis_cc_tdata,
m_axis_cc_tkeep=m_axis_cc_tkeep,
m_axis_cc_tvalid=m_axis_cc_tvalid,
m_axis_cc_tready=m_axis_cc_tready,
m_axis_cc_tlast=m_axis_cc_tlast,
m_axis_cc_tuser=m_axis_cc_tuser,
m_axil_awaddr=m_axil_awaddr,
m_axil_awprot=m_axil_awprot,
m_axil_awvalid=m_axil_awvalid,
m_axil_awready=m_axil_awready,
m_axil_wdata=m_axil_wdata,
m_axil_wstrb=m_axil_wstrb,
m_axil_wvalid=m_axil_wvalid,
m_axil_wready=m_axil_wready,
m_axil_bresp=m_axil_bresp,
m_axil_bvalid=m_axil_bvalid,
m_axil_bready=m_axil_bready,
m_axil_araddr=m_axil_araddr,
m_axil_arprot=m_axil_arprot,
m_axil_arvalid=m_axil_arvalid,
m_axil_arready=m_axil_arready,
m_axil_rdata=m_axil_rdata,
m_axil_rresp=m_axil_rresp,
m_axil_rvalid=m_axil_rvalid,
m_axil_rready=m_axil_rready,
completer_id=completer_id,
completer_id_enable=completer_id_enable,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor)
@always(delay(4))
def clkgen():
clk.next = not clk
status_error_cor_asserted = Signal(bool(0))
status_error_uncor_asserted = Signal(bool(0))
@always(clk.posedge)
def monitor():
if (status_error_cor):
status_error_cor_asserted.next = 1
if (status_error_uncor):
status_error_uncor_asserted.next = 1
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
completer_id.next = int(pcie_us.PcieId(4, 5, 6))
yield clk.posedge
print("test 1: baseline")
current_test.next = 1
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
yield delay(100)
yield clk.posedge
print("test 2: memory write")
current_test.next = 2
tlp = pcie_us.TLP_us()
tlp.fmt_type = pcie_us.TLP_MEM_WRITE
tlp.requester_id = pcie_us.PcieId(1, 2, 3)
tlp.tag = cur_tag
tlp.tc = 0
tlp.set_be_data(0x0000, b'\x11\x22\x33\x44')
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
yield delay(100)
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
assert not status_error_cor_asserted
assert not status_error_uncor_asserted
cur_tag = (cur_tag + 1) % 32
yield delay(100)
yield clk.posedge
print("test 3: IO write")
current_test.next = 3
tlp = pcie_us.TLP_us()
tlp.fmt_type = pcie_us.TLP_IO_WRITE
tlp.requester_id = pcie_us.PcieId(1, 2, 3)
tlp.tag = cur_tag
tlp.tc = 0
tlp.set_be_data(0x0000, b'\x11\x22\x33\x44')
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
print(rx_tlp)
assert rx_tlp.status == pcie_us.CPL_STATUS_SC
assert rx_tlp.tag == cur_tag
assert rx_tlp.completer_id == pcie_us.PcieId(4, 5, 6)
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
assert not status_error_cor_asserted
assert not status_error_uncor_asserted
cur_tag = (cur_tag + 1) % 32
yield delay(100)
yield clk.posedge
print("test 4: memory read")
current_test.next = 4
tlp = pcie_us.TLP_us()
tlp.fmt_type = pcie_us.TLP_MEM_READ
tlp.requester_id = pcie_us.PcieId(1, 2, 3)
tlp.tag = cur_tag
tlp.tc = 0
tlp.length = 1
tlp.set_be(0x0000, 4)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
print(rx_tlp)
data = rx_tlp.get_data()
print(data)
assert data == b'\x11\x22\x33\x44'
assert rx_tlp.status == pcie_us.CPL_STATUS_SC
assert rx_tlp.tag == cur_tag
assert rx_tlp.completer_id == pcie_us.PcieId(4, 5, 6)
assert not status_error_cor_asserted
assert not status_error_uncor_asserted
cur_tag = (cur_tag + 1) % 32
yield delay(100)
yield clk.posedge
print("test 5: IO read")
current_test.next = 5
tlp = pcie_us.TLP_us()
tlp.fmt_type = pcie_us.TLP_IO_READ
tlp.requester_id = pcie_us.PcieId(1, 2, 3)
tlp.tag = cur_tag
tlp.tc = 0
tlp.length = 1
tlp.set_be(0x0000, 4)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
print(rx_tlp)
data = rx_tlp.get_data()
print(data)
assert data == b'\x11\x22\x33\x44'
assert rx_tlp.status == pcie_us.CPL_STATUS_SC
assert rx_tlp.tag == cur_tag
assert rx_tlp.completer_id == pcie_us.PcieId(4, 5, 6)
assert not status_error_cor_asserted
assert not status_error_uncor_asserted
cur_tag = (cur_tag + 1) % 32
yield delay(100)
yield clk.posedge
print("test 6: various writes")
current_test.next = 6
for length in range(1, 5):
for offset in range(4, 8 - length + 1):
axil_ram_inst.write_mem(256 * (16 * offset + length),
b'\xAA' * 32)
tlp = pcie_us.TLP_us()
tlp.fmt_type = pcie_us.TLP_MEM_WRITE
tlp.requester_id = pcie_us.PcieId(1, 2, 3)
tlp.tag = cur_tag
tlp.tc = 0
tlp.set_be_data(256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44'[0:length])
tlp.address = 256 * (16 * offset + length) + offset
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
yield delay(100)
data = axil_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44'[0:length]
assert axil_ram_inst.read_mem(
256 * (16 * offset + length) + offset - 1, 1) == b'\xAA'
assert axil_ram_inst.read_mem(
256 * (16 * offset + length) + offset + length,
1) == b'\xAA'
assert not status_error_cor_asserted
assert not status_error_uncor_asserted
cur_tag = (cur_tag + 1) % 32
yield delay(100)
yield clk.posedge
print("test 7: various reads")
current_test.next = 7
for length in range(1, 5):
for offset in range(4, 8 - length + 1):
tlp = pcie_us.TLP_us()
tlp.fmt_type = pcie_us.TLP_MEM_READ
tlp.requester_id = pcie_us.PcieId(1, 2, 3)
tlp.tag = cur_tag
tlp.tc = 0
tlp.length = 1
tlp.set_be(256 * (16 * offset + length) + offset, length)
tlp.address = 256 * (16 * offset + length) + offset
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt,
AXIS_PCIE_DATA_WIDTH)
print(rx_tlp)
data = rx_tlp.get_data()
print(data)
assert data == b'\xAA' * (offset - 4) + b'\x11\x22\x33\x44'[
0:length] + b'\xAA' * (8 - offset - length)
assert rx_tlp.status == pcie_us.CPL_STATUS_SC
assert rx_tlp.tag == cur_tag
assert rx_tlp.completer_id == pcie_us.PcieId(4, 5, 6)
assert not status_error_cor_asserted
assert not status_error_uncor_asserted
cur_tag = (cur_tag + 1) % 32
yield delay(100)
yield clk.posedge
print("test 8: bad memory write")
current_test.next = 8
tlp = pcie_us.TLP_us()
tlp.fmt_type = pcie_us.TLP_MEM_WRITE
tlp.requester_id = pcie_us.PcieId(1, 2, 3)
tlp.tag = cur_tag
tlp.tc = 0
tlp.set_be_data(0x0000, bytearray(range(64)))
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
yield delay(100)
assert not status_error_cor_asserted
assert status_error_uncor_asserted
status_error_uncor_asserted.next = 0
cur_tag = (cur_tag + 1) % 32
yield delay(100)
yield clk.posedge
print("test 9: bad memory read")
current_test.next = 9
tlp = pcie_us.TLP_us()
tlp.fmt_type = pcie_us.TLP_MEM_READ
tlp.requester_id = pcie_us.PcieId(1, 2, 3)
tlp.tag = cur_tag
tlp.tc = 0
tlp.set_be(0x0000, 64)
tlp.address = 0x0000
cq_source.send(tlp.pack_us_cq(AXIS_PCIE_DATA_WIDTH))
yield cc_sink.wait(500)
pkt = cc_sink.recv()
rx_tlp = pcie_us.TLP_us().unpack_us_cc(pkt, AXIS_PCIE_DATA_WIDTH)
print(rx_tlp)
assert rx_tlp.status == pcie_us.CPL_STATUS_CA
assert rx_tlp.tag == cur_tag
assert rx_tlp.completer_id == pcie_us.PcieId(4, 5, 6)
assert status_error_cor_asserted
assert not status_error_uncor_asserted
cur_tag = (cur_tag + 1) % 32
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ADDR_WIDTH = 32
S_DATA_WIDTH = 32
S_STRB_WIDTH = (S_DATA_WIDTH / 8)
M_DATA_WIDTH = 32
M_STRB_WIDTH = (M_DATA_WIDTH / 8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
s_axil_awprot = Signal(intbv(0)[3:])
s_axil_awvalid = Signal(bool(0))
s_axil_wdata = Signal(intbv(0)[S_DATA_WIDTH:])
s_axil_wstrb = Signal(intbv(0)[S_STRB_WIDTH:])
s_axil_wvalid = Signal(bool(0))
s_axil_bready = Signal(bool(0))
s_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:])
s_axil_arprot = Signal(intbv(0)[3:])
s_axil_arvalid = Signal(bool(0))
s_axil_rready = Signal(bool(0))
m_axil_awready = Signal(bool(0))
m_axil_wready = Signal(bool(0))
m_axil_bresp = Signal(intbv(0)[2:])
m_axil_bvalid = Signal(bool(0))
m_axil_arready = Signal(bool(0))
m_axil_rdata = Signal(intbv(0)[M_DATA_WIDTH:])
m_axil_rresp = Signal(intbv(0)[2:])
m_axil_rvalid = Signal(bool(0))
# Outputs
s_axil_awready = Signal(bool(0))
s_axil_wready = Signal(bool(0))
s_axil_bresp = Signal(intbv(0)[2:])
s_axil_bvalid = Signal(bool(0))
s_axil_arready = Signal(bool(0))
s_axil_rdata = Signal(intbv(0)[S_DATA_WIDTH:])
s_axil_rresp = Signal(intbv(0)[2:])
s_axil_rvalid = Signal(bool(0))
m_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axil_awprot = Signal(intbv(0)[3:])
m_axil_awvalid = Signal(bool(0))
m_axil_wdata = Signal(intbv(0)[M_DATA_WIDTH:])
m_axil_wstrb = Signal(intbv(0)[M_STRB_WIDTH:])
m_axil_wvalid = Signal(bool(0))
m_axil_bready = Signal(bool(0))
m_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axil_arprot = Signal(intbv(0)[3:])
m_axil_arvalid = Signal(bool(0))
m_axil_rready = Signal(bool(0))
# AXIl4 master
axil_master_inst = axil.AXILiteMaster()
axil_master_pause = Signal(bool(False))
axil_master_logic = axil_master_inst.create_logic(
clk,
rst,
m_axil_awaddr=s_axil_awaddr,
m_axil_awprot=s_axil_awprot,
m_axil_awvalid=s_axil_awvalid,
m_axil_awready=s_axil_awready,
m_axil_wdata=s_axil_wdata,
m_axil_wstrb=s_axil_wstrb,
m_axil_wvalid=s_axil_wvalid,
m_axil_wready=s_axil_wready,
m_axil_bresp=s_axil_bresp,
m_axil_bvalid=s_axil_bvalid,
m_axil_bready=s_axil_bready,
m_axil_araddr=s_axil_araddr,
m_axil_arprot=s_axil_arprot,
m_axil_arvalid=s_axil_arvalid,
m_axil_arready=s_axil_arready,
m_axil_rdata=s_axil_rdata,
m_axil_rresp=s_axil_rresp,
m_axil_rvalid=s_axil_rvalid,
m_axil_rready=s_axil_rready,
pause=axil_master_pause,
name='master')
# AXIl4 RAM model
axil_ram_inst = axil.AXILiteRam(2**16)
axil_ram_pause = Signal(bool(False))
axil_ram_port0 = axil_ram_inst.create_port(clk,
s_axil_awaddr=m_axil_awaddr,
s_axil_awprot=m_axil_awprot,
s_axil_awvalid=m_axil_awvalid,
s_axil_awready=m_axil_awready,
s_axil_wdata=m_axil_wdata,
s_axil_wstrb=m_axil_wstrb,
s_axil_wvalid=m_axil_wvalid,
s_axil_wready=m_axil_wready,
s_axil_bresp=m_axil_bresp,
s_axil_bvalid=m_axil_bvalid,
s_axil_bready=m_axil_bready,
s_axil_araddr=m_axil_araddr,
s_axil_arprot=m_axil_arprot,
s_axil_arvalid=m_axil_arvalid,
s_axil_arready=m_axil_arready,
s_axil_rdata=m_axil_rdata,
s_axil_rresp=m_axil_rresp,
s_axil_rvalid=m_axil_rvalid,
s_axil_rready=m_axil_rready,
pause=axil_ram_pause,
name='port0')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axil_awaddr=s_axil_awaddr,
s_axil_awprot=s_axil_awprot,
s_axil_awvalid=s_axil_awvalid,
s_axil_awready=s_axil_awready,
s_axil_wdata=s_axil_wdata,
s_axil_wstrb=s_axil_wstrb,
s_axil_wvalid=s_axil_wvalid,
s_axil_wready=s_axil_wready,
s_axil_bresp=s_axil_bresp,
s_axil_bvalid=s_axil_bvalid,
s_axil_bready=s_axil_bready,
s_axil_araddr=s_axil_araddr,
s_axil_arprot=s_axil_arprot,
s_axil_arvalid=s_axil_arvalid,
s_axil_arready=s_axil_arready,
s_axil_rdata=s_axil_rdata,
s_axil_rresp=s_axil_rresp,
s_axil_rvalid=s_axil_rvalid,
s_axil_rready=s_axil_rready,
m_axil_awaddr=m_axil_awaddr,
m_axil_awprot=m_axil_awprot,
m_axil_awvalid=m_axil_awvalid,
m_axil_awready=m_axil_awready,
m_axil_wdata=m_axil_wdata,
m_axil_wstrb=m_axil_wstrb,
m_axil_wvalid=m_axil_wvalid,
m_axil_wready=m_axil_wready,
m_axil_bresp=m_axil_bresp,
m_axil_bvalid=m_axil_bvalid,
m_axil_bready=m_axil_bready,
m_axil_araddr=m_axil_araddr,
m_axil_arprot=m_axil_arprot,
m_axil_arvalid=m_axil_arvalid,
m_axil_arready=m_axil_arready,
m_axil_rdata=m_axil_rdata,
m_axil_rresp=m_axil_rresp,
m_axil_rvalid=m_axil_rvalid,
m_axil_rready=m_axil_rready)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while not axil_master_inst.idle():
yield clk.posedge
def wait_pause_master():
while not axil_master_inst.idle():
axil_master_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axil_master_pause.next = False
yield clk.posedge
def wait_pause_slave():
while not axil_master_inst.idle():
axil_ram_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axil_ram_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: write")
current_test.next = 1
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_master_inst.init_write(addr, test_data)
yield axil_master_inst.wait()
yield clk.posedge
data = axil_ram_inst.read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(addr, len(test_data)) == test_data
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_ram_inst.write_mem(addr, test_data)
axil_master_inst.init_read(addr, len(test_data))
yield axil_master_inst.wait()
yield clk.posedge
data = axil_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4, 8):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d" % (length, offset))
addr = 256 * (16 * offset + length) + offset
test_data = bytearray([x % 256 for x in range(length)])
axil_ram_inst.write_mem(addr & 0xffffff80,
b'\xAA' * (length + 256))
axil_master_inst.init_write(addr, test_data)
yield wait()
yield clk.posedge
data = axil_ram_inst.read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(addr, length) == test_data
assert axil_ram_inst.read_mem(addr - 1, 1) == b'\xAA'
assert axil_ram_inst.read_mem(addr + length, 1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4, 8):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d" % (length, offset))
addr = 256 * (16 * offset + length) + offset
test_data = bytearray([x % 256 for x in range(length)])
axil_ram_inst.write_mem(addr, test_data)
axil_master_inst.init_read(addr, length)
yield wait()
yield clk.posedge
data = axil_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
XFCP_ID_TYPE = 0x0001
XFCP_ID_STR = "AXIL Master"
XFCP_EXT_ID = 0
XFCP_EXT_ID_STR = ""
COUNT_SIZE = 16
DATA_WIDTH = 32
ADDR_WIDTH = 32
STRB_WIDTH = (DATA_WIDTH / 8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
up_xfcp_in_tdata = Signal(intbv(0)[8:])
up_xfcp_in_tvalid = Signal(bool(0))
up_xfcp_in_tlast = Signal(bool(0))
up_xfcp_in_tuser = Signal(bool(0))
up_xfcp_out_tready = Signal(bool(0))
m_axil_awready = Signal(bool(0))
m_axil_wready = Signal(bool(0))
m_axil_bresp = Signal(intbv(0)[2:])
m_axil_bvalid = Signal(bool(0))
m_axil_arready = Signal(bool(0))
m_axil_rdata = Signal(intbv(0)[DATA_WIDTH:])
m_axil_rresp = Signal(intbv(0)[2:])
m_axil_rvalid = Signal(bool(0))
# Outputs
up_xfcp_in_tready = Signal(bool(0))
up_xfcp_out_tdata = Signal(intbv(0)[8:])
up_xfcp_out_tvalid = Signal(bool(0))
up_xfcp_out_tlast = Signal(bool(0))
up_xfcp_out_tuser = Signal(bool(0))
m_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axil_awprot = Signal(intbv(0)[3:])
m_axil_awvalid = Signal(bool(0))
m_axil_wdata = Signal(intbv(0)[DATA_WIDTH:])
m_axil_wstrb = Signal(intbv(0)[STRB_WIDTH:])
m_axil_wvalid = Signal(bool(0))
m_axil_bready = Signal(bool(0))
m_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axil_arprot = Signal(intbv(0)[3:])
m_axil_arvalid = Signal(bool(0))
m_axil_rready = Signal(bool(0))
# XFCP ports
up_xfcp_port_out_pause = Signal(bool(0))
up_xfcp_port_in_pause = Signal(bool(0))
up_xfcp_port = xfcp.XFCPPort()
up_xfcp_port_logic = up_xfcp_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=up_xfcp_out_tdata,
xfcp_in_tvalid=up_xfcp_out_tvalid,
xfcp_in_tready=up_xfcp_out_tready,
xfcp_in_tlast=up_xfcp_out_tlast,
xfcp_in_tuser=up_xfcp_out_tuser,
xfcp_out_tdata=up_xfcp_in_tdata,
xfcp_out_tvalid=up_xfcp_in_tvalid,
xfcp_out_tready=up_xfcp_in_tready,
xfcp_out_tlast=up_xfcp_in_tlast,
xfcp_out_tuser=up_xfcp_in_tuser,
pause_source=up_xfcp_port_in_pause,
pause_sink=up_xfcp_port_out_pause,
name='up_xfcp_port')
# AXI4-Lite RAM model
axil_ram_inst = axil.AXILiteRam(2**16)
axil_ram_pause = Signal(bool(False))
axil_ram_port0 = axil_ram_inst.create_port(clk,
s_axil_awaddr=m_axil_awaddr,
s_axil_awprot=m_axil_awprot,
s_axil_awvalid=m_axil_awvalid,
s_axil_awready=m_axil_awready,
s_axil_wdata=m_axil_wdata,
s_axil_wstrb=m_axil_wstrb,
s_axil_wvalid=m_axil_wvalid,
s_axil_wready=m_axil_wready,
s_axil_bresp=m_axil_bresp,
s_axil_bvalid=m_axil_bvalid,
s_axil_bready=m_axil_bready,
s_axil_araddr=m_axil_araddr,
s_axil_arprot=m_axil_arprot,
s_axil_arvalid=m_axil_arvalid,
s_axil_arready=m_axil_arready,
s_axil_rdata=m_axil_rdata,
s_axil_rresp=m_axil_rresp,
s_axil_rvalid=m_axil_rvalid,
s_axil_rready=m_axil_rready,
pause=axil_ram_pause,
name='port0')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
up_xfcp_in_tdata=up_xfcp_in_tdata,
up_xfcp_in_tvalid=up_xfcp_in_tvalid,
up_xfcp_in_tready=up_xfcp_in_tready,
up_xfcp_in_tlast=up_xfcp_in_tlast,
up_xfcp_in_tuser=up_xfcp_in_tuser,
up_xfcp_out_tdata=up_xfcp_out_tdata,
up_xfcp_out_tvalid=up_xfcp_out_tvalid,
up_xfcp_out_tready=up_xfcp_out_tready,
up_xfcp_out_tlast=up_xfcp_out_tlast,
up_xfcp_out_tuser=up_xfcp_out_tuser,
m_axil_awaddr=m_axil_awaddr,
m_axil_awprot=m_axil_awprot,
m_axil_awvalid=m_axil_awvalid,
m_axil_awready=m_axil_awready,
m_axil_wdata=m_axil_wdata,
m_axil_wstrb=m_axil_wstrb,
m_axil_wvalid=m_axil_wvalid,
m_axil_wready=m_axil_wready,
m_axil_bresp=m_axil_bresp,
m_axil_bvalid=m_axil_bvalid,
m_axil_bready=m_axil_bready,
m_axil_araddr=m_axil_araddr,
m_axil_arprot=m_axil_arprot,
m_axil_arvalid=m_axil_arvalid,
m_axil_arready=m_axil_arready,
m_axil_rdata=m_axil_rdata,
m_axil_rresp=m_axil_rresp,
m_axil_rvalid=m_axil_rvalid,
m_axil_rready=m_axil_rready)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
i = 4
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle(
) or m_axil_awvalid or m_axil_wvalid or m_axil_bvalid or m_axil_arvalid or m_axil_rvalid:
i = 4
yield clk.posedge
def wait_pause_source():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle(
) or m_axil_awvalid or m_axil_wvalid or m_axil_bvalid or m_axil_arvalid or m_axil_rvalid:
i = 2
up_xfcp_port_in_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_in_pause.next = False
yield clk.posedge
def wait_pause_sink():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle(
) or m_axil_awvalid or m_axil_wvalid or m_axil_bvalid or m_axil_arvalid or m_axil_rvalid:
i = 2
up_xfcp_port_out_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_out_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test write")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x12
pkt.payload = bytearray(struct.pack('<IH', 0, 4) + b'\x11\x22\x33\x44')
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 0, 4)
yield delay(100)
yield clk.posedge
print("test 2: test read")
current_test.next = 2
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x10
pkt.payload = bytearray(struct.pack('<IH', 0, 4))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 0,
4) + b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4):
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x12
pkt.payload = bytearray(
struct.pack('<IH', 256 *
(16 * offset + length) + offset, length) +
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
data = axil_ram_inst.read_mem(256 * (16 * offset + length),
32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(
256 * (16 * offset + length) + offset, length
) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack(
'<IH', 256 * (16 * offset + length) + offset, length)
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x10
pkt.payload = bytearray(
struct.pack('<IH', 256 * (16 * offset + length) + offset,
length))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack(
'<IH', 256 * (16 * offset + length) + offset,
length) + b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 5: test trailing padding")
current_test.next = 5
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0x12
pkt1.payload = bytearray(struct.pack('<IH', 7, 1) + b'\xAA')
pkt2 = xfcp.XFCPFrame()
pkt2.ptype = 0x12
pkt2.payload = bytearray(
struct.pack('<IH', 8, 1) + b'\xBB' + b'\x00' * 8)
pkt3 = xfcp.XFCPFrame()
pkt3.ptype = 0x10
pkt3.payload = bytearray(struct.pack('<IH', 7, 1) + b'\x00' * 8)
pkt4 = xfcp.XFCPFrame()
pkt4.ptype = 0x10
pkt4.payload = bytearray(struct.pack('<IH', 7, 1) + b'\x00' * 1)
pkt5 = xfcp.XFCPFrame()
pkt5.ptype = 0x12
pkt5.payload = bytearray(struct.pack('<IH', 9, 1) + b'\xCC')
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
up_xfcp_port.send(pkt3)
up_xfcp_port.send(pkt4)
up_xfcp_port.send(pkt5)
yield clk.posedge
yield wait()
yield clk.posedge
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(7, 3) == b'\xAA\xBB\xCC'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1)
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 8, 1)
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1) + b'\xAA'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1) + b'\xAA'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 9, 1)
yield delay(100)
yield clk.posedge
print("test 6: test id")
current_test.next = 6
pkt = xfcp.XFCPFrame()
pkt.ptype = 0xFE
pkt.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 7: test id with trailing bytes")
current_test.next = 7
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0xFE
pkt1.payload = b'\0' * 256
pkt2 = xfcp.XFCPFrame()
pkt2.ptype = 0xFE
pkt2.payload = b'\0' * 8
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 8: test with rpath")
current_test.next = 8
pkt1 = xfcp.XFCPFrame()
pkt1.rpath = [1, 2, 3]
pkt1.ptype = 0xFE
pkt1.payload = b'\0' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.rpath = [4, 5, 6]
pkt2.ptype = 0x10
pkt2.payload = bytearray(struct.pack('<IH', 0, 4))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [1, 2, 3]
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [4, 5, 6]
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 0,
4) + b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 9: test invalid packets")
current_test.next = 9
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0x99
pkt1.payload = b'\x00' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.path = [0]
pkt2.ptype = 0xFE
pkt2.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
assert rx_pkt is None
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
FILTER_LEN = 4
DATA_WIDTH = 32
ADDR_WIDTH = 16
STRB_WIDTH = (DATA_WIDTH/8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
i2c_scl_i = Signal(bool(1))
i2c_sda_i = Signal(bool(1))
m_axil_awready = Signal(bool(0))
m_axil_wready = Signal(bool(0))
m_axil_bresp = Signal(intbv(0)[2:])
m_axil_bvalid = Signal(bool(0))
m_axil_arready = Signal(bool(0))
m_axil_rdata = Signal(intbv(0)[DATA_WIDTH:])
m_axil_rresp = Signal(intbv(0)[2:])
m_axil_rvalid = Signal(bool(0))
enable = Signal(bool(0))
device_address = Signal(intbv(0)[7:])
m_scl_i = Signal(bool(1))
m_sda_i = Signal(bool(1))
s2_scl_i = Signal(bool(1))
s2_sda_i = Signal(bool(1))
# Outputs
i2c_scl_o = Signal(bool(1))
i2c_scl_t = Signal(bool(1))
i2c_sda_o = Signal(bool(1))
i2c_sda_t = Signal(bool(1))
m_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axil_awprot = Signal(intbv(0)[3:])
m_axil_awvalid = Signal(bool(0))
m_axil_wdata = Signal(intbv(0)[DATA_WIDTH:])
m_axil_wstrb = Signal(intbv(0)[STRB_WIDTH:])
m_axil_wvalid = Signal(bool(0))
m_axil_bready = Signal(bool(0))
m_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axil_arprot = Signal(intbv(0)[3:])
m_axil_arvalid = Signal(bool(0))
m_axil_rready = Signal(bool(0))
busy = Signal(bool(0))
bus_addressed = Signal(bool(0))
bus_active = Signal(bool(0))
m_scl_o = Signal(bool(1))
m_scl_t = Signal(bool(1))
m_sda_o = Signal(bool(1))
m_sda_t = Signal(bool(1))
s2_scl_o = Signal(bool(1))
s2_scl_t = Signal(bool(1))
s2_sda_o = Signal(bool(1))
s2_sda_t = Signal(bool(1))
# I2C master
i2c_master_inst = i2c.I2CMaster()
i2c_master_logic = i2c_master_inst.create_logic(
clk,
rst,
scl_i=m_scl_i,
scl_o=m_scl_o,
scl_t=m_scl_t,
sda_i=m_sda_i,
sda_o=m_sda_o,
sda_t=m_sda_t,
prescale=4,
name='master'
)
# I2C memory model 2
i2c_mem_inst2 = i2c.I2CMem(1024)
i2c_mem_logic2 = i2c_mem_inst2.create_logic(
scl_i=s2_scl_i,
scl_o=s2_scl_o,
scl_t=s2_scl_t,
sda_i=s2_sda_i,
sda_o=s2_sda_o,
sda_t=s2_sda_t,
abw=2,
address=0x51,
latency=0,
name='slave2'
)
# AXI4-Lite RAM model
axil_ram_inst = axil.AXILiteRam(2**16)
axil_ram_pause = Signal(bool(False))
axil_ram_port0 = axil_ram_inst.create_port(
clk,
s_axil_awaddr=m_axil_awaddr,
s_axil_awprot=m_axil_awprot,
s_axil_awvalid=m_axil_awvalid,
s_axil_awready=m_axil_awready,
s_axil_wdata=m_axil_wdata,
s_axil_wstrb=m_axil_wstrb,
s_axil_wvalid=m_axil_wvalid,
s_axil_wready=m_axil_wready,
s_axil_bresp=m_axil_bresp,
s_axil_bvalid=m_axil_bvalid,
s_axil_bready=m_axil_bready,
s_axil_araddr=m_axil_araddr,
s_axil_arprot=m_axil_arprot,
s_axil_arvalid=m_axil_arvalid,
s_axil_arready=m_axil_arready,
s_axil_rdata=m_axil_rdata,
s_axil_rresp=m_axil_rresp,
s_axil_rvalid=m_axil_rvalid,
s_axil_rready=m_axil_rready,
pause=axil_ram_pause,
name='port0'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
i2c_scl_i=i2c_scl_i,
i2c_scl_o=i2c_scl_o,
i2c_scl_t=i2c_scl_t,
i2c_sda_i=i2c_sda_i,
i2c_sda_o=i2c_sda_o,
i2c_sda_t=i2c_sda_t,
m_axil_awaddr=m_axil_awaddr,
m_axil_awprot=m_axil_awprot,
m_axil_awvalid=m_axil_awvalid,
m_axil_awready=m_axil_awready,
m_axil_wdata=m_axil_wdata,
m_axil_wstrb=m_axil_wstrb,
m_axil_wvalid=m_axil_wvalid,
m_axil_wready=m_axil_wready,
m_axil_bresp=m_axil_bresp,
m_axil_bvalid=m_axil_bvalid,
m_axil_bready=m_axil_bready,
m_axil_araddr=m_axil_araddr,
m_axil_arprot=m_axil_arprot,
m_axil_arvalid=m_axil_arvalid,
m_axil_arready=m_axil_arready,
m_axil_rdata=m_axil_rdata,
m_axil_rresp=m_axil_rresp,
m_axil_rvalid=m_axil_rvalid,
m_axil_rready=m_axil_rready,
busy=busy,
bus_addressed=bus_addressed,
bus_active=bus_active,
enable=enable,
device_address=device_address
)
@always_comb
def bus():
# emulate I2C wired AND
scl = m_scl_o & i2c_scl_o & s2_scl_o
sda = m_sda_o & i2c_sda_o & s2_sda_o
m_scl_i.next = scl;
m_sda_i.next = sda;
i2c_scl_i.next = scl
i2c_sda_i.next = sda
s2_scl_i.next = scl
s2_sda_i.next = sda
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
enable.next = 1
device_address.next = 0x50
yield clk.posedge
print("test 1: write")
current_test.next = 1
i2c_master_inst.init_write(0x50, b'\x00\x04'+b'\x11\x22\x33\x44')
yield i2c_master_inst.wait()
yield clk.posedge
while busy:
yield clk.posedge
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axil_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
i2c_master_inst.init_write(0x50, b'\x00\x04')
i2c_master_inst.init_read(0x50, 4)
yield i2c_master_inst.wait()
yield clk.posedge
data = i2c_master_inst.get_read_data()
assert data[0] == 0x50
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1,9):
for offset in range(4):
i2c_master_inst.init_write(0x50, bytearray(struct.pack('>H', 256*(16*offset+length)+offset)+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]))
yield i2c_master_inst.wait()
yield clk.posedge
while busy:
yield clk.posedge
data = axil_ram_inst.read_mem(256*(16*offset+length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axil_ram_inst.read_mem(256*(16*offset+length)+offset,length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1,9):
for offset in range(4):
i2c_master_inst.init_write(0x50, bytearray(struct.pack('>H', 256*(16*offset+length)+offset)))
i2c_master_inst.init_read(0x50, length)
yield i2c_master_inst.wait()
yield clk.posedge
data = i2c_master_inst.get_read_data()
assert data[0] == 0x50
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
# TODO various reads and writes
# yield clk.posedge
# print("test 3: read with delays")
# current_test.next = 3
# i2c_master_inst.init_write(0x50, b'\x00\x04')
# i2c_master_inst.init_read(0x50, 4)
# data_source.send(b'\x11\x22\x33\x44')
# data_source_pause.next = True
# data_sink_pause.next = True
# yield delay(5000)
# data_sink_pause.next = False
# yield delay(2000)
# data_source_pause.next = False
# yield i2c_master_inst.wait()
# yield clk.posedge
# data = None
# while not data:
# yield clk.posedge
# data = data_sink.recv()
# assert data.data == b'\x00\x04'
# data = i2c_master_inst.get_read_data()
# assert data[0] == 0x50
# assert data[1] == b'\x11\x22\x33\x44'
# yield delay(100)
yield clk.posedge
print("test 4: access slave 2")
current_test.next = 4
i2c_master_inst.init_write(0x51, b'\x00\x04'+b'\x11\x22\x33\x44')
yield i2c_master_inst.wait()
yield clk.posedge
data = i2c_mem_inst2.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert i2c_mem_inst2.read_mem(4,4) == b'\x11\x22\x33\x44'
i2c_master_inst.init_write(0x51, b'\x00\x04')
i2c_master_inst.init_read(0x51, 4)
yield i2c_master_inst.wait()
yield clk.posedge
data = i2c_master_inst.get_read_data()
assert data[0] == 0x51
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
S_COUNT = 4
M_COUNT = 4
DATA_WIDTH = 32
ADDR_WIDTH = 32
STRB_WIDTH = (DATA_WIDTH/8)
M_REGIONS = 1
M_BASE_ADDR = [0x00000000, 0x01000000, 0x02000000, 0x03000000]
M_ADDR_WIDTH = [24]*M_COUNT*M_REGIONS
M_CONNECT_READ = [0b1111]*M_COUNT
M_CONNECT_WRITE = [0b1111]*M_COUNT
M_SECURE = 0b0000
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axil_awaddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)]
s_axil_awprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
s_axil_awvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axil_wdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
s_axil_wstrb_list = [Signal(intbv(0)[STRB_WIDTH:]) for i in range(S_COUNT)]
s_axil_wvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axil_bready_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axil_araddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)]
s_axil_arprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
s_axil_arvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axil_rready_list = [Signal(bool(0)) for i in range(S_COUNT)]
m_axil_awready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axil_wready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axil_bresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)]
m_axil_bvalid_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axil_arready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axil_rdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(M_COUNT)]
m_axil_rresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)]
m_axil_rvalid_list = [Signal(bool(0)) for i in range(M_COUNT)]
s_axil_awaddr = ConcatSignal(*reversed(s_axil_awaddr_list))
s_axil_awprot = ConcatSignal(*reversed(s_axil_awprot_list))
s_axil_awvalid = ConcatSignal(*reversed(s_axil_awvalid_list))
s_axil_wdata = ConcatSignal(*reversed(s_axil_wdata_list))
s_axil_wstrb = ConcatSignal(*reversed(s_axil_wstrb_list))
s_axil_wvalid = ConcatSignal(*reversed(s_axil_wvalid_list))
s_axil_bready = ConcatSignal(*reversed(s_axil_bready_list))
s_axil_araddr = ConcatSignal(*reversed(s_axil_araddr_list))
s_axil_arprot = ConcatSignal(*reversed(s_axil_arprot_list))
s_axil_arvalid = ConcatSignal(*reversed(s_axil_arvalid_list))
s_axil_rready = ConcatSignal(*reversed(s_axil_rready_list))
m_axil_awready = ConcatSignal(*reversed(m_axil_awready_list))
m_axil_wready = ConcatSignal(*reversed(m_axil_wready_list))
m_axil_bresp = ConcatSignal(*reversed(m_axil_bresp_list))
m_axil_bvalid = ConcatSignal(*reversed(m_axil_bvalid_list))
m_axil_arready = ConcatSignal(*reversed(m_axil_arready_list))
m_axil_rdata = ConcatSignal(*reversed(m_axil_rdata_list))
m_axil_rresp = ConcatSignal(*reversed(m_axil_rresp_list))
m_axil_rvalid = ConcatSignal(*reversed(m_axil_rvalid_list))
# Outputs
s_axil_awready = Signal(intbv(0)[S_COUNT:])
s_axil_wready = Signal(intbv(0)[S_COUNT:])
s_axil_bresp = Signal(intbv(0)[S_COUNT*2:])
s_axil_bvalid = Signal(intbv(0)[S_COUNT:])
s_axil_arready = Signal(intbv(0)[S_COUNT:])
s_axil_rdata = Signal(intbv(0)[S_COUNT*DATA_WIDTH:])
s_axil_rresp = Signal(intbv(0)[S_COUNT*2:])
s_axil_rvalid = Signal(intbv(0)[S_COUNT:])
m_axil_awaddr = Signal(intbv(0)[M_COUNT*ADDR_WIDTH:])
m_axil_awprot = Signal(intbv(0)[M_COUNT*3:])
m_axil_awvalid = Signal(intbv(0)[M_COUNT:])
m_axil_wdata = Signal(intbv(0)[M_COUNT*DATA_WIDTH:])
m_axil_wstrb = Signal(intbv(0)[M_COUNT*STRB_WIDTH:])
m_axil_wvalid = Signal(intbv(0)[M_COUNT:])
m_axil_bready = Signal(intbv(0)[M_COUNT:])
m_axil_araddr = Signal(intbv(0)[M_COUNT*ADDR_WIDTH:])
m_axil_arprot = Signal(intbv(0)[M_COUNT*3:])
m_axil_arvalid = Signal(intbv(0)[M_COUNT:])
m_axil_rready = Signal(intbv(0)[M_COUNT:])
s_axil_awready_list = [s_axil_awready(i) for i in range(S_COUNT)]
s_axil_wready_list = [s_axil_wready(i) for i in range(S_COUNT)]
s_axil_bresp_list = [s_axil_bresp((i+1)*2, i*2) for i in range(S_COUNT)]
s_axil_bvalid_list = [s_axil_bvalid(i) for i in range(S_COUNT)]
s_axil_arready_list = [s_axil_arready(i) for i in range(S_COUNT)]
s_axil_rdata_list = [s_axil_rdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(S_COUNT)]
s_axil_rresp_list = [s_axil_rresp((i+1)*2, i*2) for i in range(S_COUNT)]
s_axil_rvalid_list = [s_axil_rvalid(i) for i in range(S_COUNT)]
m_axil_awaddr_list = [m_axil_awaddr((i+1)*ADDR_WIDTH, i*ADDR_WIDTH) for i in range(M_COUNT)]
m_axil_awprot_list = [m_axil_awprot((i+1)*3, i*3) for i in range(M_COUNT)]
m_axil_awvalid_list = [m_axil_awvalid(i) for i in range(M_COUNT)]
m_axil_wdata_list = [m_axil_wdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(M_COUNT)]
m_axil_wstrb_list = [m_axil_wstrb((i+1)*STRB_WIDTH, i*STRB_WIDTH) for i in range(M_COUNT)]
m_axil_wvalid_list = [m_axil_wvalid(i) for i in range(M_COUNT)]
m_axil_bready_list = [m_axil_bready(i) for i in range(M_COUNT)]
m_axil_araddr_list = [m_axil_araddr((i+1)*ADDR_WIDTH, i*ADDR_WIDTH) for i in range(M_COUNT)]
m_axil_arprot_list = [m_axil_arprot((i+1)*3, i*3) for i in range(M_COUNT)]
m_axil_arvalid_list = [m_axil_arvalid(i) for i in range(M_COUNT)]
m_axil_rready_list = [m_axil_rready(i) for i in range(M_COUNT)]
# AXI4-Lite masters
axil_master_inst_list = []
axil_master_pause_list = []
axil_master_logic = []
for k in range(S_COUNT):
m = axil.AXILiteMaster()
p = Signal(bool(False))
axil_master_inst_list.append(m)
axil_master_pause_list.append(p)
axil_master_logic.append(m.create_logic(
clk,
rst,
m_axil_awaddr=s_axil_awaddr_list[k],
m_axil_awprot=s_axil_awprot_list[k],
m_axil_awvalid=s_axil_awvalid_list[k],
m_axil_awready=s_axil_awready_list[k],
m_axil_wdata=s_axil_wdata_list[k],
m_axil_wstrb=s_axil_wstrb_list[k],
m_axil_wvalid=s_axil_wvalid_list[k],
m_axil_wready=s_axil_wready_list[k],
m_axil_bresp=s_axil_bresp_list[k],
m_axil_bvalid=s_axil_bvalid_list[k],
m_axil_bready=s_axil_bready_list[k],
m_axil_araddr=s_axil_araddr_list[k],
m_axil_arprot=s_axil_arprot_list[k],
m_axil_arvalid=s_axil_arvalid_list[k],
m_axil_arready=s_axil_arready_list[k],
m_axil_rdata=s_axil_rdata_list[k],
m_axil_rresp=s_axil_rresp_list[k],
m_axil_rvalid=s_axil_rvalid_list[k],
m_axil_rready=s_axil_rready_list[k],
pause=p,
name='master_%d' % k
))
# AXI4-Lite RAM models
axil_ram_inst_list = []
axil_ram_pause_list = []
axil_ram_logic = []
for k in range(M_COUNT):
r = axil.AXILiteRam(2**16)
p = Signal(bool(False))
axil_ram_inst_list.append(r)
axil_ram_pause_list.append(p)
axil_ram_logic.append(r.create_port(
clk,
s_axil_awaddr=m_axil_awaddr_list[k],
s_axil_awprot=m_axil_awprot_list[k],
s_axil_awvalid=m_axil_awvalid_list[k],
s_axil_awready=m_axil_awready_list[k],
s_axil_wdata=m_axil_wdata_list[k],
s_axil_wstrb=m_axil_wstrb_list[k],
s_axil_wvalid=m_axil_wvalid_list[k],
s_axil_wready=m_axil_wready_list[k],
s_axil_bresp=m_axil_bresp_list[k],
s_axil_bvalid=m_axil_bvalid_list[k],
s_axil_bready=m_axil_bready_list[k],
s_axil_araddr=m_axil_araddr_list[k],
s_axil_arprot=m_axil_arprot_list[k],
s_axil_arvalid=m_axil_arvalid_list[k],
s_axil_arready=m_axil_arready_list[k],
s_axil_rdata=m_axil_rdata_list[k],
s_axil_rresp=m_axil_rresp_list[k],
s_axil_rvalid=m_axil_rvalid_list[k],
s_axil_rready=m_axil_rready_list[k],
pause=p,
latency=1,
name='ram_%d' % k
))
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axil_awaddr=s_axil_awaddr,
s_axil_awprot=s_axil_awprot,
s_axil_awvalid=s_axil_awvalid,
s_axil_awready=s_axil_awready,
s_axil_wdata=s_axil_wdata,
s_axil_wstrb=s_axil_wstrb,
s_axil_wvalid=s_axil_wvalid,
s_axil_wready=s_axil_wready,
s_axil_bresp=s_axil_bresp,
s_axil_bvalid=s_axil_bvalid,
s_axil_bready=s_axil_bready,
s_axil_araddr=s_axil_araddr,
s_axil_arprot=s_axil_arprot,
s_axil_arvalid=s_axil_arvalid,
s_axil_arready=s_axil_arready,
s_axil_rdata=s_axil_rdata,
s_axil_rresp=s_axil_rresp,
s_axil_rvalid=s_axil_rvalid,
s_axil_rready=s_axil_rready,
m_axil_awaddr=m_axil_awaddr,
m_axil_awprot=m_axil_awprot,
m_axil_awvalid=m_axil_awvalid,
m_axil_awready=m_axil_awready,
m_axil_wdata=m_axil_wdata,
m_axil_wstrb=m_axil_wstrb,
m_axil_wvalid=m_axil_wvalid,
m_axil_wready=m_axil_wready,
m_axil_bresp=m_axil_bresp,
m_axil_bvalid=m_axil_bvalid,
m_axil_bready=m_axil_bready,
m_axil_araddr=m_axil_araddr,
m_axil_arprot=m_axil_arprot,
m_axil_arvalid=m_axil_arvalid,
m_axil_arready=m_axil_arready,
m_axil_rdata=m_axil_rdata,
m_axil_rresp=m_axil_rresp,
m_axil_rvalid=m_axil_rvalid,
m_axil_rready=m_axil_rready
)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]):
yield clk.posedge
def wait_pause_master():
while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]):
for k in range(S_COUNT):
axil_master_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
axil_master_pause_list[k].next = False
yield clk.posedge
def wait_pause_slave():
while not all([axil_master_inst_list[k].idle() for k in range(S_COUNT)]):
for k in range(M_COUNT):
axil_ram_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(M_COUNT):
axil_ram_pause_list[k].next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: write")
current_test.next = 1
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_master_inst_list[0].init_write(addr, test_data)
yield axil_master_inst_list[0].wait()
yield clk.posedge
data = axil_ram_inst_list[0].read_mem(addr&0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axil_ram_inst_list[0].read_mem(addr, len(test_data)) == test_data
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
addr = 4
test_data = b'\x11\x22\x33\x44'
axil_ram_inst_list[0].write_mem(addr, test_data)
axil_master_inst_list[0].init_read(addr, len(test_data))
yield axil_master_inst_list[0].wait()
yield clk.posedge
data = axil_master_inst_list[0].get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 3: one to many")
current_test.next = 3
addr = 4
test_data = b'\x11\x22\x33\x44'
for k in range(S_COUNT):
axil_master_inst_list[0].init_write(addr+M_BASE_ADDR[k], test_data)
yield axil_master_inst_list[0].wait()
yield clk.posedge
for k in range(S_COUNT):
data = axil_ram_inst_list[k].read_mem(addr&0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
for k in range(S_COUNT):
assert axil_ram_inst_list[k].read_mem(addr, len(test_data)) == test_data
for k in range(S_COUNT):
axil_master_inst_list[0].init_read(addr+M_BASE_ADDR[k], len(test_data))
yield axil_master_inst_list[0].wait()
yield clk.posedge
for k in range(S_COUNT):
data = axil_master_inst_list[0].get_read_data()
assert data[0] == addr+M_BASE_ADDR[k]
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 4: many to one")
current_test.next = 4
for k in range(M_COUNT):
axil_master_inst_list[k].init_write(k*4, bytearray([(k+1)*17]*4))
for k in range(M_COUNT):
yield axil_master_inst_list[k].wait()
yield clk.posedge
data = axil_ram_inst_list[0].read_mem(addr&0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
for k in range(M_COUNT):
assert axil_ram_inst_list[0].read_mem(k*4, 4) == bytearray([(k+1)*17]*4)
for k in range(M_COUNT):
axil_master_inst_list[k].init_read(k*4, 4)
for k in range(M_COUNT):
yield axil_master_inst_list[k].wait()
yield clk.posedge
for k in range(M_COUNT):
data = axil_master_inst_list[k].get_read_data()
assert data[0] == k*4
assert data[1] == bytearray([(k+1)*17]*4)
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in range(1,8):
for offset in range(4,8):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d"% (length, offset))
addr = 256*(16*offset+length)+offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_ram_inst_list[0].write_mem(256*(16*offset+length), b'\xAA'*32)
axil_master_inst_list[0].init_write(addr, test_data)
yield wait()
yield clk.posedge
data = axil_ram_inst_list[0].read_mem(256*(16*offset+length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axil_ram_inst_list[0].read_mem(addr, length) == test_data
assert axil_ram_inst_list[0].read_mem(addr-1, 1) == b'\xAA'
assert axil_ram_inst_list[0].read_mem(addr+length, 1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in range(1,8):
for offset in range(4,8):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d"% (length, offset))
addr = 256*(16*offset+length)+offset
test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
axil_master_inst_list[0].init_read(addr, length)
yield wait()
yield clk.posedge
data = axil_master_inst_list[0].get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 7: concurrent operations")
current_test.next = 7
for count in [1, 2, 4, 8]:
for stride in [2, 3, 5, 7]:
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("count %d, stride %d"% (count, stride))
for k in range(S_COUNT):
for l in range(count):
ram = ((k*61+l)*stride)%M_COUNT
offset = k*256+l*4
axil_ram_inst_list[ram].write_mem(offset, b'\xAA'*4)
axil_master_inst_list[k].init_write(M_BASE_ADDR[ram]+offset, bytearray([0xaa, k, l, 0xaa]))
ram = ((k*61+l+67)*stride)%M_COUNT
offset = k*256+l*4
axil_ram_inst_list[ram].write_mem(offset+0x8000, bytearray([0xaa, k, l, 0xaa]))
axil_master_inst_list[k].init_read(M_BASE_ADDR[ram]+offset+0x8000, 4)
yield wait()
yield clk.posedge
for k in range(S_COUNT):
for l in range(count):
ram = ((k*61+l)*stride)%M_COUNT
offset = k*256+l*4
axil_ram_inst_list[ram].read_mem(offset, 4) == bytearray([0xaa, k, l, 0xaa])
ram = ((k*61+l+67)*stride)%M_COUNT
offset = k*256+l*4
data = axil_master_inst_list[k].get_read_data()
assert data[0] == M_BASE_ADDR[ram]+offset+0x8000
assert data[1] == bytearray([0xaa, k, l, 0xaa])
yield delay(100)
yield clk.posedge
print("test 8: bad write")
current_test.next = 8
axil_master_inst_list[0].init_write(0xff000000, b'\xDE\xAD\xBE\xEF')
yield axil_master_inst_list[0].wait()
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 9: bad read")
current_test.next = 9
axil_master_inst_list[0].init_read(0xff000000, 4)
yield axil_master_inst_list[0].wait()
yield clk.posedge
data = axil_master_inst_list[0].get_read_data()
assert data[0] == 0xff000000
yield delay(100)
raise StopSimulation
return instances()