def setUp(self):
fw_path = get_basil_dir() + "/firmware/modules"
cocotb_compile_and_run(
[
fw_path + "/gpio/gpio.v",
fw_path + "/utils/reset_gen.v",
fw_path + "/utils/bus_to_ip.v",
fw_path + "/rrp_arbiter/rrp_arbiter.v",
fw_path + "/utils/ODDR_sim.v",
fw_path + "/utils/generic_fifo.v",
fw_path + "/utils/cdc_pulse_sync.v",
fw_path + "/utils/fx2_to_bus.v",
fw_path + "/pulse_gen/pulse_gen.v",
fw_path + "/pulse_gen/pulse_gen_core.v",
fw_path + "/sram_fifo/sram_fifo_core.v",
fw_path + "/sram_fifo/sram_fifo.v",
os.path.dirname(__file__) + "/../firmware/src/sram_test.v",
os.path.dirname(__file__) + "/../tests/tb.v",
],
top_level="tb",
sim_bus="basil.utils.sim.SiLibUsbBusDriver",
)
with open(os.path.dirname(__file__) + "/../sram_test.yaml", "r") as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg["transfer_layer"][0]["type"] = "SiSim"
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'),
os.path.join(fw_path, 'utils/ODDR_sim.v'),
os.path.join(fw_path, 'utils/generic_fifo.v'),
os.path.join(fw_path, 'utils/cdc_pulse_sync.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(fw_path, 'pulse_gen/pulse_gen.v'),
os.path.join(fw_path, 'pulse_gen/pulse_gen_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
os.path.join(os.path.dirname(__file__),
'../firmware/src/sram_test.v'),
os.path.join(os.path.dirname(__file__), '../tests/tb.v')
],
top_level='tb',
sim_bus='basil.utils.sim.SiLibUsbBusDriver')
with open(os.path.join(os.path.dirname(__file__), '../sram_test.yaml'),
'r') as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'),
os.path.join(fw_path, 'utils/ODDR_sim.v'),
os.path.join(fw_path, 'utils/generic_fifo.v'),
os.path.join(fw_path, 'utils/cdc_pulse_sync.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(fw_path, 'pulse_gen/pulse_gen.v'),
os.path.join(fw_path, 'pulse_gen/pulse_gen_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
os.path.join(os.path.dirname(__file__), '../firmware/src/sram_test.v'),
os.path.join(os.path.dirname(__file__), '../tests/tb.v')],
top_level='tb',
sim_bus='basil.utils.sim.SiLibUsbBusDriver'
)
with open(os.path.join(os.path.dirname(__file__), '../sram_test.yaml'), 'r') as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'gpio/gpio_core.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'),
os.path.join(fw_path, 'utils/ODDR_sim.v'),
os.path.join(fw_path, 'utils/generic_fifo.v'),
os.path.join(fw_path, 'utils/cdc_pulse_sync.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(fw_path, 'utils/BUFG_sim.v'),
os.path.join(fw_path, 'utils/cdc_syncfifo.v'),
os.path.join(fw_path, 'utils/ddr_des.v'),
os.path.join(fw_path, 'utils/IDDR_sim.v'),
os.path.join(fw_path, 'utils/DCM_sim.v'),
os.path.join(fw_path, 'utils/clock_divider.v'),
os.path.join(fw_path, 'utils/clock_multiplier.v'),
os.path.join(fw_path, 'utils/flag_domain_crossing.v'),
os.path.join(fw_path, 'utils/3_stage_synchronizer.v'),
os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx.v'),
os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx_core.v'),
os.path.join(fw_path, 'seq_gen/seq_gen.v'),
os.path.join(fw_path, 'seq_gen/seq_gen_core.v'),
os.path.join(fw_path, 'tdc_s3/tdc_s3.v'),
os.path.join(fw_path, 'tdc_s3/tdc_s3_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
os.path.join(os.path.dirname(__file__),
'../firmware/src/clk_gen.v'),
os.path.join(os.path.dirname(__file__), '../firmware/src/pixel.v'),
os.path.join(os.path.dirname(__file__), '../tests/tb.v')
],
top_level='tb',
sim_bus='basil.utils.sim.SiLibUsbBusDriver')
with open(os.path.join(os.path.dirname(__file__), '../pixel.yaml'),
'r') as f:
cnfg = yaml.safe_load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = pixel.Pixel(cnfg)
self.chip.init()
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'),
os.path.join(fw_path, 'utils/ODDR_sim.v'),
os.path.join(fw_path, 'utils/generic_fifo.v'),
os.path.join(fw_path, 'utils/cdc_pulse_sync.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(fw_path, 'utils/BUFG_sim.v'),
os.path.join(fw_path, 'utils/cdc_syncfifo.v'),
os.path.join(fw_path, 'utils/ddr_des.v'),
os.path.join(fw_path, 'utils/IDDR_sim.v'),
os.path.join(fw_path, 'utils/DCM_sim.v'),
os.path.join(fw_path, 'utils/clock_divider.v'),
os.path.join(fw_path, 'utils/clock_multiplier.v'),
os.path.join(fw_path, 'utils/flag_domain_crossing.v'),
os.path.join(fw_path, 'utils/3_stage_synchronizer.v'),
os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx.v'),
os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx_core.v'),
os.path.join(fw_path, 'seq_gen/seq_gen.v'),
os.path.join(fw_path, 'seq_gen/seq_gen_core.v'),
os.path.join(fw_path, 'tdc_s3/tdc_s3.v'),
os.path.join(fw_path, 'tdc_s3/tdc_s3_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
os.path.join(os.path.dirname(__file__), '../firmware/src/clk_gen.v'),
os.path.join(os.path.dirname(__file__), '../firmware/src/pixel.v'),
os.path.join(os.path.dirname(__file__), '../tests/tb.v')],
top_level='tb',
sim_bus='basil.utils.sim.SiLibUsbBusDriver'
)
with open(os.path.join(os.path.dirname(__file__), '../pixel.yaml'), 'r') as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = pixel.Pixel(cnfg)
self.chip.init()
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(os.path.dirname(__file__), '../src/example.v')],
top_level='example',
sim_bus='basil.utils.sim.SiLibUsbBusDriver'
)
with open(os.path.join(os.path.dirname(__file__), 'example.yaml'), 'r') as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(os.path.dirname(__file__), '../src/example.v')
],
top_level='example',
sim_bus='basil.utils.sim.SiLibUsbBusDriver')
with open(os.path.join(os.path.dirname(__file__), 'example.yaml'),
'r') as f:
cnfg = yaml.safe_load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
fw_path = get_basil_dir() + "/firmware/modules"
cocotb_compile_and_run(
[
fw_path + "/gpio/gpio.v",
fw_path + "/utils/reset_gen.v",
fw_path + "/utils/bus_to_ip.v",
fw_path + "/utils/fx2_to_bus.v",
os.path.dirname(__file__) + "/../src/example.v",
],
top_level="example",
sim_bus="basil.utils.sim.SiLibUsbBusDriver",
)
with open(os.path.dirname(__file__) + "/example.yaml", "r") as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg["transfer_layer"][0]["type"] = "SiSim"
self.chip = Dut(cnfg)
self.chip.init()
