TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.

• TAPA explicitly decouples communication and computation for better QoR.

• TAPA integrates the AutoBridge floorplanner to optimize the RTL generation process.

• TAPA achieves 2× higher the frequency on average compared to Vivado. ¹

• TAPA compiles 7× faster than Vitis HLS. ²

• TAPA provides 3× faster software simulation than Vitis HLS.²

• TAPA provides 8× faster RTL simulation than Vitis.

• [in-progress] TAPA is integrating RapidStream that is up to 10× faster than Vivado.³

• TAPA extends the Vitis HLS syntax for richer expressiveness at the C++ level.

• TAPA provides dedicated APIs for arbitrary external memory access patterns.

• TAPA allows users to explicitly specify parallelism.

• In addition to static burst analysis, TAPA supports runtime burst detectuion by transparently merging small memory transactions into large bursts.

• TAPA significantly reduce the area overhead of HBM interface IPs compared to Vitis HLS.

• TAPA includes an automated design space exploration tool to balance the resource pressure and the wire pressure for HBM FPGAs.

• TAPA automatically select the physical channel for each top-level argument of your accelerator.

• Serpens, DAC'22, achieves 270 MHz on the Xilinx Alveo U280 HBM board when using 24 HBM channels. The Vitis HLS baseline failed in routing.
• Sextans, FPGA'22, achieves 260 MHz on the Xilinx Alveo U250 board when using 4 DDR channels. The Vivado baseline achieves only 189 MHz.
• SPLAG, FPGA'22, achieves up to a 4.9× speedup over state-of-the-art FPGA accelerators, up to a 2.6× speedup over 32-thread CPU running at 4.4 GHz, and up to a 0.9× speedup over an A100 GPU (that has 4.1× power budget and 3.4× HBM bandwidth).
• AutoSA Systolic-Array Compiler, FPGA'21:
• KNN, FPT'20, achieves 252 MHz on the Xilinx Alveo U280 board. The Vivado baseline achieves only 165 MHz.

• Documentation
• Installation
• Hello World
• API Reference

• Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong. Extending High-Level Synthesis for Task-Parallel Programs. In FCCM, 2021. [PDF] [Code] [Slides] [Video]
• Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong. AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. In FPGA, 2021. (Best Paper Award) [PDF] [Code] [Slides] [Video]