This library contains universal HDL AST nodes (Hardware Description Language Abstract Syntax Tree = objects for representation of code constructs) for SystemVerilog, VHDL and others. This AST can be generated from SV/VHDL code by hdlConvertor and it can also be converted to VHDL/SV/JSON/SystemC/... and other formats using hdlConvertorAst.to module. Note that the conversion of AST of different languages requires an extra care. E. g. the VHDL AST and SV AST will have a different type names and thus the direct transpilation using hdlConvertorAst.to module will not yield working code. If source and target language differs the translation is required. For this translations and post processing you can use hdlConvertorAst.translate module

Doc shared with hdlConvertor.

• code generators
• code parsers
• document generators
• compilers/transpilers

• IEEE 1076-2008 (VHDL 2008) and all previous standard, (currently without tool_directive and PSL)
• IEEE 1800-2017 (SystemVerilog 2017) and all previous standards.
• SystemC 2.3.3
• HdlConvertor JSON
• pycocotb basic_rtl_sim_model (python interpreted RTL simulator)
• hwt (hardware construction framework (HCL) with algorithmic synthesis (HLS))

• single straightforward universal AST for all languages, wide spectrum of import/export languages
• automatic parenthesis resolution in expressions based on operator priority/associativity
• clever white-spaces, constant and expression formating
• comments preserved as doc of objects

# note this may be older version than you see in repo
sudo pip3 install hdlConvertorAst

# or download repository and run
sudo python3 setup.py install

# if you are using version from git rather uninstall
# old library first if required
# sudo pip3 uninstall hdlConvertorAst