def time_load1000000(self): l3 = Cache(4096, 1024, 8, "LRU") l2 = Cache(4096, 8, 8, "LRU", parent=l3) l1 = Cache(512, 8, 8, "LRU", parent=l2) mh = CacheSimulator(l1) with Timer() as t: mh.load(0, 1000000) return t.interval
def time_load100000_tiny_collisions(self): l3 = Cache(4, 8, 8, "LRU") l2 = Cache(4, 4, 8, "LRU", parent=l3) l1 = Cache(2, 4, 8, "LRU", parent=l2) mh = CacheSimulator(l1) mh.load(0, 100000) with Timer() as t: mh.load(0, 100000) return t.interval
def test_fill(self): l3 = Cache(4, 8, 8,"LRU") l2 = Cache(4, 4, 8,"LRU", parent=l3) l1 = Cache(2, 4, 8,"LRU", parent=l2) mem = MainMemory(l3) mh = CacheSimulator(l1, mem) mh.load(0, 512) mh.load(448, 576) self.assertEqual(l1.cached, set(range(512, 576))) self.assertEqual(l2.cached, set(range(448, 576))) self.assertEqual(l3.cached, set(range(320, 576)))
def test_fill_nocl(self): l3 = Cache(4, 8, 1, "LRU") l2 = Cache(4, 4, 1, "LRU", parent=l3) l1 = Cache(2, 4, 1, "LRU", parent=l2) mem = MainMemory(l3) mh = CacheSimulator(l1, mem) mh.load(0, 32) mh.load(16,48) self.assertEqual(l1.cached, set(range(40,48))) self.assertEqual(l2.cached, set(range(32,48))) self.assertEqual(l3.cached, set(range(16,48)))
def test_fill(self): mem = MainMemory() l3 = Cache("L3", 4, 8, 8, "LRU") mem.load_to(l3) mem.store_from(l3) l2 = Cache("L2", 4, 4, 8, "LRU", store_to=l3, load_from=l3) l1 = Cache("L1", 2, 4, 8, "LRU", store_to=l2, load_from=l2) mh = CacheSimulator(l1, mem) mh.load(range(0, 512)) mh.load(range(448, 576)) self.assertEqual(l1.cached, set(range(512, 576))) self.assertEqual(l2.cached, set(range(448, 576))) self.assertEqual(l3.cached, set(range(320, 576)))
elif model == 3: l3 = Cache("L3", 20, 4, 64, "LRU") mem.load_to(l3) mem.store_from(l3) l2 = Cache("L2", 2, 1, 64, "LRU", store_to=l3, load_from=l3) l1 = Cache("L1", 1, 1, 64, "LRU", store_to=l2, load_from=l2) cs = CacheSimulator(l1, mem) infile = open("cachesim_output.out", "rb") while True: chunk = infile.read(9) if len(chunk) < 9: break t = chunk[0] a = int.from_bytes(chunk[1:8], byteorder='little', signed=False) if t == 0: if verbose == True: print('load ' + str(a)) cs.load(a, length=8) if t == 1: if verbose == True: print('store ' + str(a)) cs.store(a, length=8) cs.force_write_back() cs.print_stats()
sets=512, ways=8, cl_size=cacheline_size, replacement_policy="LRU", write_back=True, write_allocate=True, store_to=l3, load_from=l3, victims_to=None, swap_on_load=False) l1 = Cache(name="L1", sets=64, ways=8, cl_size=cacheline_size, replacement_policy="LRU", write_back=True, write_allocate=True, store_to=l2, load_from=l2, victims_to=None, swap_on_load=False) # inclusive/exclusive does not matter in first-level cs = CacheSimulator(first_level=l1, main_memory=mem) cs.load(23) cv = CacheVisualizer(cs, [10, 16]) cv.dump_state() # ============================= # AMD Bulldozer Exclusive Cache # ============================= cacheline_size = 64 mem = MainMemory() l3 = Cache(name="L3", sets=2048, ways=64, cl_size=cacheline_size, # 4MB replacement_policy="LRU", write_back=True, write_allocate=True, store_to=None, load_from=None, victims_to=None, swap_on_load=False) # This is a victim cache, so exclusiveness should be obvious
mem = MainMemory() #l3 = Cache("L3", 20480, 16, 64, "LRU") # 20MB: 20480 sets, 16-ways with cacheline size of 64 bytes #l2 = Cache("L2", 256, 4, 64, "LRU", store_to=l3, load_from=l3) # 256KB #l1 = Cache("L1", 64, 8, 64, "LRU", store_to=l2, load_from=l2) # 32KB # Cascade Lake l3 = Cache("L3", 28672, 11, 64, "LRU") # 28MB: 11-ways with cacheline size of 64 bytes l2 = Cache("L2", 1024, 16, 64, "LRU", store_to=l3, load_from=l3) # 1MB l1 = Cache("L1", 32, 8, 64, "LRU", store_to=l2, load_from=l2) # 32KB mem.load_to(l3) mem.store_from(l3) cs = CacheSimulator(l1, mem) with open(filename, 'r') as fp: for line in fp.readlines(): op, addr = line.split(": ") op = op[0] addr = int(addr, 16) if op == 'W': cs.store(addr, length=8) elif op == 'R': cs.load(addr, length=8) else: sys.exit("Invalid operation: {}".format(op)) cs.force_write_back() cs.print_stats()