def test_read_refs_into_cache_set_associative_lru(self):
     """read_refs_into_cache should work for set associative LRU cache"""
     refs = sim.get_addr_refs(
         word_addrs=TestReadRefs.WORD_ADDRS, num_addr_bits=8,
         num_tag_bits=5, num_index_bits=2, num_offset_bits=1)
     cache, ref_statuses = sim.read_refs_into_cache(
         refs=refs, num_sets=4, num_blocks_per_set=3,
         num_words_per_block=2, num_index_bits=2, replacement_policy='lru')
     nose.assert_dict_equal(cache, {
         '00': [
             {'tag': '01011', 'data': [88, 89]}
         ],
         '01': [
             {'tag': '00000', 'data': [2, 3]},
             {'tag': '00101', 'data': [42, 43]},
             {'tag': '10111', 'data': [186, 187]}
         ],
         '10': [
             {'tag': '10110', 'data': [180, 181]},
             {'tag': '00101', 'data': [44, 45]},
             {'tag': '11111', 'data': [252, 253]}
         ],
         '11': [
             {'tag': '10111', 'data': [190, 191]},
             {'tag': '00001', 'data': [14, 15]},
         ]
     })
     nose.assert_set_equal(self.get_hits(ref_statuses), {3, 6, 8})
 def test_read_refs_into_cache_fully_associative_mru(self):
     """read_refs_into_cache should work for fully associative MRU cache"""
     refs = sim.get_addr_refs(
         word_addrs=TestReadRefs.WORD_ADDRS, num_addr_bits=8,
         num_tag_bits=7, num_index_bits=0, num_offset_bits=1)
     cache, ref_statuses = sim.read_refs_into_cache(
         refs=refs, num_sets=1, num_blocks_per_set=4,
         num_words_per_block=2, num_index_bits=0, replacement_policy='mru')
     nose.assert_dict_equal(cache, {
         '0': [
             {'tag': '0000001', 'data': [2, 3]},
             {'tag': '1111110', 'data': [252, 253]},
             {'tag': '0010101', 'data': [42, 43]},
             {'tag': '0000111', 'data': [14, 15]}
         ]
     })
     nose.assert_set_equal(self.get_hits(ref_statuses), {3, 8})
 def test_read_refs_into_cache_direct_mapped_lru(self):
     """read_refs_into_cache should work for direct-mapped LRU cache"""
     word_addrs = [0, 8, 0, 6, 8]
     refs = sim.get_addr_refs(
         word_addrs=word_addrs, num_addr_bits=4,
         num_tag_bits=2, num_index_bits=2, num_offset_bits=0)
     cache, ref_statuses = sim.read_refs_into_cache(
         refs=refs, num_sets=4, num_blocks_per_set=1,
         num_words_per_block=1, num_index_bits=2, replacement_policy='lru')
     nose.assert_dict_equal(cache, {
         '00': [
             {'tag': '10', 'data': [8]}
         ],
         '01': [],
         '10': [
             {'tag': '01', 'data': [6]},
         ],
         '11': []
     })
     nose.assert_set_equal(self.get_hits(ref_statuses), set())