def do_add(self, arg):
"""\nAdd component to current project.
add name=<string> base=<string>
name = new component instance name.
base = component name.
"""
args = COMPONENT_ARGS.parse(arg)
if args:
try:
cp = find_component(settings.components_dir, args.base)
if cp is None:
self.write("*** No component '%s' found, component addition canceled\n" % args.base)
else:
settings.active_project.addComponent(args.name, cp)
except ProjectError, e:
self.write(e.message)
else:
self.write("Component '%s' successfully added as '%s'.\n" % (args.base, path.basename(args.name)))
def check(self, component_dir):
"""Verify project integrity.
Attributes
component_dir - Orchestra IP directory
"""
# Clean all caches
errors = {}
self._valid = True
# Verification steps
# 1. clocks
# Verify that almost 1 clock is declared
chk_errors = []
if len(self.clocks):
for clock in self.clocks.iteritems():
if(clock.frequency == 0):
chk_errors.append("*** Clock '%s' has bad frequency value." % clock.name)
else:
chk_errors.append("*** No clock domain defined.")
if chk_errors:
errors["clocks"] = chk_errors
self._valid = False
project = ProjectData(self)
project.clocks = dict([clock.name.lower(), []]
for clock in self.clocks.iteritems()
)
# 2. Wires
# Verify that at least 1 wire is defined
wire_errors = []
project.wires = dict([wire.name.lower(), ([], [])]
for wire in self.wires.iteritems()
)
if not len(project.wires):
wire_errors.append("*** No wire defined.")
# 3. components
# 3.1 Interfaces
# Verify that each clock interface is connected to a clock domain
# Verify that each master and slave interface is connected to a route
# Verify that each slave interface has a valid address
# Verify address overlapping
# 3.2 Generics
# ??????
chk_errors = []
chk_warns = []
for (cp, cp_attr) in self.components:
if project.components.has_key(cp.base):
cp_data = project.components[cp.base]
else:
# New component detected, try to load it
cp_data = find_component(component_dir, cp.base)
if not cp_data:
chk_errors.append("Component '%s' don't exist." % cp.base)
continue
# Check it's validity
if cp_data.has_errors:
errors[("IP %s" % cp.base)] = cp_data.last_errors
self._valid = False
# Save it for future use
project.components[cp.base] = cp_data
# Add component instance to list
generics = cp_attr["generics"].asDict("name","value")
instance = cp_data.asInstance(name=cp.name, generics=generics)
project.instances[cp.name] = instance
# Verify instance integrity
if instance.has_errors:
errors[("Component %s" % cp.name)] = instance.last_errors
self._valid = False
# Convert base IP interfaces to dictionary
cp_ifaces = dict([iface.name.lower(), [iface.type.upper(), False]]
for iface in cp_data.interfaces.iteritems()
)
# Check interfaces settings
for iface in cp_attr["interfaces"].iteritems():
if cp_ifaces.has_key(iface.name.lower()):
cpiface = cp_ifaces[iface.name.lower()]
if cpiface[1]:
chk_errors.append("Component '%s', duplicate interface '%s' declaration." % (cp.name, iface.name))
# Mark interface as used
cpiface[1] = True
else:
chk_errors.append("Component '%s', interface '%s' not present in base IP '%s'." % (cp.name, iface.name, cp.base))
continue
if cpiface[0] == "WBC":
if iface.offset:
chk_warns.append("Component '%s', clock interface '%s' unused parameter OFFSET." % (cp.name, iface.name))
if not iface.link:
chk_errors.append("Component '%s', clock interface '%s' not connected." % (cp.name, iface.name))
elif not self.clocks.hasElement(iface.link):
chk_errors.append("Component '%s', clock interface '%s' connected to unavailable clock '%s'." % (cp.name, iface.name, iface.link))
else:
project.clocks[iface.link.lower()].append(instance.interface(iface.name.lower()))
elif cpiface[0] == "WBM":
if iface.offset:
chk_warns.append("Component '%s', master interface '%s' unused parameter OFFSET." % (cp.name, iface.name))
if not iface.link:
chk_errors.append("Component '%s', master interface '%s' not connected." % (cp.name, iface.name))
elif not self.wires.hasElement(iface.link):
chk_errors.append("Component '%s', master interface '%s' connected to unavailable bus/wire '%s'." % (cp.name, iface.name, iface.link))
else:
wire = project.wires[iface.link.lower()]
wire[0].append(instance.interface(iface.name.lower()))
elif cpiface[0] == "WBS":
# Store interface base address as instance settings.
instance.setOffset(iface.name, iface.offset)
if not iface.link:
chk_errors.append("Component '%s', slave interface '%s' not connected." % (cp.name, iface.name))
elif not self.wires.hasElement(iface.link):
chk_errors.append("Component '%s', slave interface '%s' connected to unavailable bus/wire '%s'." % (cp.name, iface.name, iface.link))
else:
wire = project.wires[iface.link.lower()]
wire[1].append(instance.interface(iface.name.lower()))
elif cpiface[0] == "GLS":
project.externals.append(instance.interface(iface.name.lower()))
else:
chk_errors.append("Component '%s', interface '%s' unknown type '%s'." % (cp.name, iface.name, cpiface[0]))
# Verify interfaces settings
for (ifname, ifparam) in cp_ifaces.iteritems():
if not ifparam[1]:
if ifparam[0] == "GLS":
chk_warns.append("Component '%s', globals interface '%s' not used." % (cp.name, ifname))
elif ifparam[0] == "WBC":
chk_errors.append("Component '%s', clock interface '%s' not connected." % (cp.name, ifname))
elif ifparam[0] == "WBM":
chk_errors.append("Component '%s', master interface '%s' not connected." % (cp.name, ifname))
elif ifparam[0] == "WBS":
chk_errors.append("Component '%s', slave interface '%s' not connected." % (cp.name, ifname))
else:
chk_errors.append("Component '%s', interface '%s' not used." % (cp.name, ifname))
if not self.components:
chk_errors.append("No components in project.")
if chk_errors:
self._valid = False
chk = [(("ERR: %s") % e) for e in chk_errors]
chk_errors = chk
if chk_warns:
chk = [(("WARN: %s") % w) for w in chk_warns]
chk_errors.extend(chk)
if chk_errors:
errors["Components"] = chk_errors
# 4. Verify that each wire has at least one master and one slave
for w_name, w_iface in project.wires.iteritems():
if len(w_iface[0]) == 0:
wire_errors.append("Wire '%s' has no master." % w_name)
if len(w_iface[1]) == 0:
wire_errors.append("Wire '%s' has no slave." % w_name)
if wire_errors:
errors["Wire"] = wire_errors
self._valid = False
self._errors = errors
self._settings = project
return errors
