def __init__(self, dut_conf=None): self.dut = fe65p2(dut_conf) self.dut.init() self.dut.power_up() time.sleep(0.1) self.dut['global_conf']['PrmpVbpDac'] = 36 self.dut['global_conf']['vthin1Dac'] = 255 self.dut['global_conf']['vthin2Dac'] = 0 self.dut['global_conf']['vffDac'] = 42 self.dut['global_conf']['PrmpVbnFolDac'] = 51 self.dut['global_conf']['vbnLccDac'] = 1 self.dut['global_conf']['compVbnDac'] = 25 self.dut['global_conf']['preCompVbnDac'] = 50 self.dut['global_conf']['Latency'] = 400 # chip['global_conf']['ColEn'][0] = 1 self.dut['global_conf']['ColEn'].setall(True) self.dut['global_conf']['ColSrEn'].setall(True) # enable programming of all columns self.dut['global_conf']['ColSrOut'] = 15 self.dut['global_conf']['OneSr'] = 0 # all multi columns in parallel self.dut.write_global() self.dut['control']['RESET'] = 0b10 self.dut['control'].write() self.working_dir = os.path.join(os.getcwd(), "output_data") if not os.path.exists(self.working_dir): os.makedirs(self.working_dir)
def __init__(self, dut_conf=None): self.dut = fe65p2(dut_conf) self.dut.init() self.dut.power_up() time.sleep(0.1) self.dut['global_conf']['PrmpVbpDac'] = 36 self.dut['global_conf']['vthin1Dac'] = 255 self.dut['global_conf']['vthin2Dac'] = 0 self.dut['global_conf']['vffDac'] = 42 self.dut['global_conf']['PrmpVbnFolDac'] = 51 self.dut['global_conf']['vbnLccDac'] = 1 self.dut['global_conf']['compVbnDac'] = 25 self.dut['global_conf']['preCompVbnDac'] = 50 self.dut['global_conf']['Latency'] = 400 # chip['global_conf']['ColEn'][0] = 1 self.dut['global_conf']['ColEn'].setall(True) self.dut['global_conf']['ColSrEn'].setall(True) # enable programming of all columns self.dut['global_conf']['ColSrOut'] = 15 self.dut['global_conf']['OneSr'] = 0 # all multi columns in parallel self.dut.write_global() self.dut['control']['RESET'] = 0b10 self.dut['control'].write() self.working_dir = os.path.join(os.getcwd(), "output_data") if not os.path.exists(self.working_dir): os.makedirs(self.working_dir)
def test_sr(self, mock_preprocess):
self.dut = fe65p2()
self.dut.init()
self.dut['control']['RESET'] = 1
self.dut['control'].write()
self.dut['control']['RESET'] = 0
self.dut['control'].write()
#global reg
self.dut['global_conf']['PrmpVbpDac'] = 36
self.dut['global_conf']['vthin1Dac'] = 255
self.dut['global_conf']['vthin2Dac'] = 0
self.dut['global_conf']['PrmpVbnFolDac'] = 0
self.dut['global_conf']['vbnLccDac'] = 51
self.dut['global_conf']['compVbnDac'] = 25
self.dut['global_conf']['preCompVbnDac'] = 50
self.dut['global_conf']['ColSrEn'].setall(
True) #enable programming of all columns
self.dut.write_global()
self.dut.write_global()
send = self.dut['global_conf'].tobytes()
rec = self.dut['global_conf'].get_data(size=19)
self.assertEqual(send, rec)
#pixel reg
self.dut['pixel_conf'][0] = 1
self.dut.write_pixel()
self.dut['control']['RESET'] = 0b11
self.dut['control'].write()
def test_sr(self, mock_preprocess):
self.dut = fe65p2()
self.dut.init()
#reset SPI memory
self.dut['global_conf'].set_size(8*19)
self.dut['global_conf'].write()
while not self.dut['global_conf'].is_ready:
pass
self.dut['global_conf'].write()
while not self.dut['global_conf'].is_ready:
pass
self.dut['control']['RESET'] = 1
self.dut['control'].write()
self.dut['control']['RESET'] = 0
self.dut['control'].write()
#global reg
self.dut['global_conf']['PrmpVbpDac'] = 36
self.dut['global_conf']['vthin1Dac'] = 255
self.dut['global_conf']['vthin2Dac'] = 0
self.dut['global_conf']['PrmpVbnFolDac'] = 0
self.dut['global_conf']['vbnLccDac'] = 51
self.dut['global_conf']['compVbnDac'] = 25
self.dut['global_conf']['preCompVbnDac'] = 50
self.dut['global_conf']['ColSrEn'].setall(True) #enable programming of all columns
self.dut.write_global()
self.dut.write_global()
send = self.dut['global_conf'].tobytes()
rec = self.dut['global_conf'].get_data(size=19)
self.assertEqual(send,rec)
self.dut['control']['RESET'] = 0b11
self.dut['control'].write()
