def _declr(self): addClkRstn(self) with self._paramsShared(): self.subunit0 = SimpleUnitAxiStream() self.a0 = AxiStream() self.b0 = AxiStream()._m()
def _declr(self): addClkRstn(self) with self._paramsShared(): self.dataIn = AxiStream() self.conv0 = AxiSToLocalLink() self.conv1 = LocalLinkToAxiS() self.dataOut = AxiStream()._m()
def _declr(self): with self._paramsShared(): self.a = AxiStream() self.b0 = AxiStream()._m() self.b1 = AxiStream()._m() self.u0 = UnitWithArrIntf()
def _declr(self): with self._paramsShared(): if self.HAS_TX: self.tx = AxiStream() if self.HAS_RX: self.rx = AxiStream(masterDir=DIRECTION.IN)
def _declr(self): self.headers = AxiStream() self.patternMatch = AxiStream() self.din = AxiStream() self.dout = AxiStream()._m() self.cfg = Axi4Lite()
def _declr(self): addClkRstn(self) with self._paramsShared(): self.a0 = AxiStream() self.b0 = AxiStream()._m() self.u0 = Simple2withNonDirectIntConnection() self.u1 = Simple2withNonDirectIntConnection()
def _declr(self): addClkRstn(self) LEN = 2 with self._paramsShared(): self.a = HObjList(AxiStream() for _ in range(LEN)) self.b = HObjList(AxiStream() for _ in range(LEN))._m() self.u0 = SimpleSubunit() self.u1 = SimpleSubunit()
def _declr(self): addClkRstn(self) self.myIp = Signal(dtype=ipv4_t) with self._paramsShared(exclude={self.USE_STRB}): self.rx = AxiStream() with self._paramsShared(): self.tx = AxiStream()._m()
def _declr(self): assert self.USE_STRB addClkRstn(self) with self._paramsShared(): self.dataIn = AxiStream() with self._paramsShared(exclude=({"DATA_WIDTH"}, set())): o = self.dataOut = AxiStream()._m() o.DATA_WIDTH = self.OUT_DATA_WIDTH
def _config(self): self.T = Param(HStruct( (HStream(Bits(8), frame_len=(1, inf), start_offsets=[0]), "f0"), (HStream(Bits(16), frame_len=(1, 1)), "f1"), )) AxiStream._config(self) self.DATA_WIDTH = 16 self.USE_KEEP = True self.OUT_OFFSET = Param(0)
def _declr(self): addClkRstn(self) with self._paramsShared(): self.din = AxiStream() self.export = AxiStream()._m() self.cfg = Axi4Lite() self.hfe = HeadFieldExtractor() self.patternMatch = PatternMatch() self.filter = Filter() self.exporter = Exporter()
def _declr(self): addClkRstn(self) with self._paramsShared(): self.a = AxiStream() self.b0 = AxiStream()._m() self.b1 = AxiStream()._m() self.u0 = Simple2withNonDirectIntConnection() self.u1 = UnitWithArrIntf() self.u2_0 = Simple2withNonDirectIntConnection() self.u2_1 = Simple2withNonDirectIntConnection()
def apply(self, dtype: HdlType, field_path: Optional[TypePath] = None) -> Interface: """ Run the connversion """ if isinstance(dtype, HStream): assert dtype.element_t == Bits(8), dtype assert dtype.start_offsets == (0, ), dtype.start_offsets assert dtype.len_min >= 1, dtype i = AxiStream() i.DATA_WIDTH = 8 else: i = super(HdlType_to_Interface_with_AxiStream, self).apply(dtype, field_path) return i
def _mkFieldIntf(self, parent: Union[StructIntf, UnionSource], structField: HStructField): t = structField.dtype path = parent._field_path / structField.name if isinstance(t, HUnion): i = UnionSource(t, path, parent._instantiateFieldFn) i._fieldsToInterfaces = parent._fieldsToInterfaces return i elif isinstance(t, HStruct): i = StructIntf(t, path, parent._instantiateFieldFn) i._fieldsToInterfaces = parent._fieldsToInterfaces return i elif isinstance(t, HStream): if self.SHARED_READY: raise NotImplementedError(t) else: i = AxiStream() i._updateParamsFrom(self) return i else: if self.SHARED_READY: i = VldSynced() else: i = Handshaked() i.DATA_WIDTH = structField.dtype.bit_length() return i
def _declr(self): assert self.USE_KEEP t = self.T assert isinstance(t, HStruct) word_bytes = self.word_bytes = self.DATA_WIDTH // 8 input_cnt = self.input_cnt = len(t.fields) streams = [f.dtype for f in t.fields] fju = FrameAlignmentUtils(word_bytes, self.OUT_OFFSET) input_B_dst = fju.resolve_input_bytes_destinations( streams) self.state_trans_table = input_B_dst_to_fsm( word_bytes, input_cnt, input_B_dst) addClkRstn(self) with self._paramsShared(): self.dataOut = AxiStream()._m() self.dataIn = HObjList(AxiStream() for _ in range(self.input_cnt))
def connect_r(self, s_r: RamHsR, axi: Axi4, r_cntr: RtlSignal, CNTR_MAX: int, in_axi_t: Union[HStruct, HUnion]): self.addr_defaults(axi.ar) # rm id from r channel as it is not currently supported in frame parser r_tmp = AxiStream() r_tmp.USE_STRB = False r_tmp.DATA_WIDTH = axi.r.DATA_WIDTH self.r_tmp = r_tmp r_tmp(axi.r, exclude=( axi.r.id, axi.r.resp, )) r_data = AxiSBuilder(self, r_tmp)\ .parse(in_axi_t).data if self.data_words_in_axi_word <= 1: self.connect_addr(s_r.addr.data, axi.ar.addr) s_r.data.data(r_data.data[s_r.DATA_WIDTH:]) ar_sn = StreamNode([s_r.addr], [axi.ar]) r_sn = StreamNode([r_data], [s_r.data]) else: addr, sub_addr = self.split_subaddr(s_r.addr.data) self.connect_addr(addr, axi.ar.addr) sel = HsBuilder(self, r_data._select, master_to_slave=False)\ .buff(self.MAX_TRANS_OVERLAP).end sel.data(sub_addr) data_items = [ getattr(r_data, f"data{i:d}").data for i in range(self.data_words_in_axi_word) ] r_data_selected = HsBuilder.join_prioritized(self, data_items).end s_r.data.data(r_data_selected.data) ar_sn = StreamNode([s_r.addr], [axi.ar, sel]) r_sn = StreamNode([r_data_selected], [s_r.data]) ar_sn.sync(r_cntr != CNTR_MAX) r_sn.sync() r_en = r_sn.ack() If(axi.ar.ready & axi.ar.valid, If(~r_en, r_cntr(r_cntr + 1))).Elif(r_en, r_cntr(r_cntr - 1))
def _impl(self): # we have to register interface on this unit first before use with self._paramsShared(): self.b = AxiStream() b = self.b b(self.a) self.c(b)
def _declr(self): with self._paramsShared(): # user requests self.req = AddrSizeHs() with self._paramsShared(exclude={self.ID_WIDTH}): self.w = AxiStream() ack = self.ack = Handshaked(masterDir=DIRECTION.IN) ack._replaceParam(ack.DATA_WIDTH, self.ID_WIDTH)
def _declr(self): addClkRstn(self) with self._paramsShared(): self.axis_out = AxiStream()._m() with self._paramsShared(prefix="CNTRL_"): self.cntrl = Axi4Lite() reg_t = Bits(self.CNTRL_DATA_WIDTH) self.conv = AxiLiteEndpoint( HStruct((reg_t, "enable"), (reg_t, "len")))
def _declr(self): addClkRstn(self) if self.INPUT_T is not None: # if INPUT_T is none it menas that the component is configured to print a costant string. self.data_in = HdlType_to_Interface_with_AxiStream().apply( self.INPUT_T) # filter out emplty strings self.FORMAT = tuple(f for f in self.FORMAT if not isinstance(f, str) or f) assert self.FORMAT, "Need to have something to print" with self._paramsShared(): self.data_out = AxiStream()._m()
def _declr(self): addClkRstn(self) with self._paramsShared(): self.dataIn = AxiStream() self.dataOut = AxiStream()._m() db = self.dataBuff = AxiSFifo() # to place fifo in bram db.DEPTH.set((self.MAX_LEN + 1) * 2) self.sizes = Handshaked()._m() self.sizes.DATA_WIDTH.set( log2ceil(self.MAX_LEN) + 1 + self.getAlignBitsCnt()) sb = self.sizesBuff = HandshakedFifo(Handshaked) sb.DEPTH.set(self.SIZES_BUFF_DEPTH) sb.DATA_WIDTH.set(self.sizes.DATA_WIDTH.get()) if self.EXPORT_ALIGNMENT_ERROR: assert self.USE_STRB, "Error can not happend when there is no validity mask for alignment" self.errorAlignment = Signal()._m() assert isPow2(self.DATA_WIDTH)
def _declr(self): addClkRstn(self) self.eth = Rmii()._m() if self.FREQ is None: self.clk.FREQ = self.eth.FREQ else: self.clk.FREQ = self.FREQ self.tx = AxiStream() self.rx = VldSyncedDataErrLast()._m() for ch in [self.rx, self.tx]: ch.DATA_WIDTH = 8
def _declr(self): with self._paramsShared(): # user requests self.req = AddrSizeHs() with self._paramsShared(exclude=({"ID_WIDTH"}, set())): self.w = AxiStream() if self.ID_WIDTH: ack = Handshaked(masterDir=DIRECTION.IN) ack.DATA_WIDTH = self.ID_WIDTH else: ack = HandshakeSync(masterDir=DIRECTION.IN) self.ack = ack
def _declr(self): assert self.USE_KEEP addClkRstn(self) with self._paramsShared(): self.dataIn = AxiStream() self.regs = HObjList(UnalignedJoinRegIntf()._m() for _ in range(self.REG_CNT)) self.keep_masks = HObjList( VectSignal(self.DATA_WIDTH // 8) for _ in range(self.REG_CNT)) # used to shift whole register pipeline using input keep_mask self.ready = Signal() if self.ID_WIDTH or self.USER_WIDTH or self.DEST_WIDTH: raise NotImplementedError("It is not clear how id/user/dest" " should be managed between the frames")
def _mkFieldIntf(parent: StructIntf, structField: HStructField): """ Instantiate interface for all members of input type """ t = structField.dtype if isinstance(t, HUnion): return UnionSink(t, parent._instantiateFieldFn) elif isinstance(t, HStruct): return StructIntf(t, parent._instantiateFieldFn) elif isinstance(t, HStream): p = AxiStream() p.DATA_WIDTH.set(structField.dtype.elmType.bit_length()) p.USE_STRB.set(True) return p else: p = Handshaked() p.DATA_WIDTH.set(structField.dtype.bit_length()) return p
def _mkFieldIntf(self, parent: StructIntf, structField: HStructField): """ Instantiate interface for all members of input type """ t = structField.dtype path = parent._field_path / structField.name if isinstance(t, HUnion): p = UnionSink(t, path, parent._instantiateFieldFn) p._fieldsToInterfaces = parent._fieldsToInterfaces elif isinstance(t, HStruct): p = StructIntf(t, path, parent._instantiateFieldFn) p._fieldsToInterfaces = parent._fieldsToInterfaces elif isinstance(t, HStream): p = AxiStream() p._updateParamsFrom(self) else: p = Handshaked() p.DATA_WIDTH = structField.dtype.bit_length() return p
def _declr(self): with self._paramsShared(): # user requests self.req = AddrSizeHs() self.r = AxiStream(masterDir=DIRECTION.IN)
def _initSimAgent(self): AxiStream._initSimAgent(self)
def _declr(self): addClkRstn(self) with self._paramsShared(): self.dataIn = AxiStream() self.dataOut = AxiStream()._m()
def _declr(self): with self._paramsShared(): self.a = AxiStream() self.b = HObjList(AxiStream() for _ in range(2))._m()
def _config(self): self.REG_CNT = Param(2) AxiStream._config(self) self.USE_KEEP = True
def _config(self): AxiStream._config(self) self.SIZES_BUFF_DEPTH = Param(16) self.MAX_LEN = Param((2048 // 8) - 1) self.EXPORT_ALIGNMENT_ERROR = Param(False)