Example #1
0
for tile in ic.ramb_tiles:
    for entry in ic.tile_db(tile[0], tile[1]):
        if entry[1] == "RamConfig":
            assert entry[2] not in ram_config_bitidx
            ram_config_bitidx[entry[2]] = ('B', entry[0])
    for entry in ic.tile_db(tile[0], tile[1]+1):
        if entry[1] == "RamConfig":
            assert entry[2] not in ram_config_bitidx
            ram_config_bitidx[entry[2]] = ('T', entry[0])
    break

for tile in ic.ramb_tiles:
    ramb_config = icebox.tileconfig(ic.tile(tile[0], tile[1]))
    ramt_config = icebox.tileconfig(ic.tile(tile[0], tile[1]+1))
    if ic.device == "8k":
        negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1"
        negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1]+1)) == "1"
    else:
        negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1"
        negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1]+1)) == "1"
    def get_ram_config(name):
        assert name in ram_config_bitidx
        if ram_config_bitidx[name][0] == 'B':
            return ramb_config.match(ram_config_bitidx[name][1])
        elif ram_config_bitidx[name][0] == 'T':
            return ramt_config.match(ram_config_bitidx[name][1])
        else:
            assert False
    def get_ram_wire(name, msb, lsb, default="1'b0"):
        wire_bits = []
        for i in range(msb, lsb-1, -1):
Example #2
0
     else:
         net_cin = seg_to_net((lut[0], lut[1], "lutff_%d/cout" % (lut[2]-1)), "0")
     carry_assigns.append([net_cout, "/* CARRY %2d %2d %2d */ (%s & %s) | ((%s | %s) & %s)" %
             (lut[0], lut[1], lut[2], net_in1, net_in2, net_in1, net_in2, net_cin)])
 if seq_bits[1] == "1":
     n = next_netname()
     text_wires.append("wire %s;" % n)
     if not strip_comments:
         text_wires.append("// FF %s" % (lut,))
         text_wires.append("")
     net_cen = seg_to_net((lut[0], lut[1], "lutff_global/cen"), "1")
     net_clk = seg_to_net((lut[0], lut[1], "lutff_global/clk"), "0")
     net_sr  = seg_to_net((lut[0], lut[1], "lutff_global/s_r"), "0")
     if seq_bits[3] == "0":
         always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s) if (%s) %s <= %s ? %s : %s;" %
                 (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos",
                 net_clk, net_cen, net_out, net_sr, seq_bits[2], n))
     else:
         always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s, posedge %s) if (%s) %s <= %s; else if (%s) %s <= %s;" %
                 (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos",
                 net_clk, net_sr, net_sr, net_out, seq_bits[2], net_cen, net_out, n))
     wire_to_reg.add(net_out)
     net_out = n
 if not "1" in lut_bits:
     const_assigns.append([net_out, "1'b0"])
 elif not "0" in lut_bits:
     const_assigns.append([net_out, "1'b1"])
 else:
     def make_lut_expr(bits, sigs):
         if not sigs:
             return "%s" % bits[0]
Example #3
0
     else:
         net_cin = seg_to_net((lut[0], lut[1], "lutff_%d/cout" % (lut[2]-1)), "1'b0")
     carry_assigns.append([net_cout, "/* CARRY %2d %2d %2d */ (%s & %s) | ((%s | %s) & %s)" %
             (lut[0], lut[1], lut[2], net_in1, net_in2, net_in1, net_in2, net_cin)])
 if seq_bits[1] == "1":
     n = next_netname()
     text_wires.append("wire %s;" % n)
     if not strip_comments:
         text_wires.append("// FF %s" % (lut,))
         text_wires.append("")
     net_cen = seg_to_net((lut[0], lut[1], "lutff_global/cen"), "1'b1")
     net_clk = seg_to_net((lut[0], lut[1], "lutff_global/clk"), "1'b0")
     net_sr  = seg_to_net((lut[0], lut[1], "lutff_global/s_r"), "1'b0")
     if seq_bits[3] == "0":
         always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s) if (%s) %s <= %s ? 1'b%s : %s;" %
                 (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos",
                 net_clk, net_cen, net_out, net_sr, seq_bits[2], n))
     else:
         always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s, posedge %s) if (%s) %s <= 1'b%s; else if (%s) %s <= %s;" %
                 (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos",
                 net_clk, net_sr, net_sr, net_out, seq_bits[2], net_cen, net_out, n))
     wire_to_reg.add(net_out)
     net_out = n
 if not "1" in lut_bits:
     const_assigns.append([net_out, "1'b0"])
 elif not "0" in lut_bits:
     const_assigns.append([net_out, "1'b1"])
 else:
     def make_lut_expr(bits, sigs):
         if not sigs:
             return "1'b%s" % bits[0]
Example #4
0
for tile in ic.ramb_tiles:
    for entry in ic.tile_db(tile[0], tile[1]):
        if entry[1] == "RamConfig":
            assert entry[2] not in ram_config_bitidx
            ram_config_bitidx[entry[2]] = ('B', entry[0])
    for entry in ic.tile_db(tile[0], tile[1]+1):
        if entry[1] == "RamConfig":
            assert entry[2] not in ram_config_bitidx
            ram_config_bitidx[entry[2]] = ('T', entry[0])
    break

for tile in ic.ramb_tiles:
    ramb_config = icebox.tileconfig(ic.tile(tile[0], tile[1]))
    ramt_config = icebox.tileconfig(ic.tile(tile[0], tile[1]+1))
    if ic.device == "8k":
        negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1"
        negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1]+1)) == "1"
    else:
        negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1"
        negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1]+1)) == "1"
    def get_ram_config(name):
        assert name in ram_config_bitidx
        if ram_config_bitidx[name][0] == 'B':
            return ramb_config.match(ram_config_bitidx[name][1])
        elif ram_config_bitidx[name][0] == 'T':
            return ramt_config.match(ram_config_bitidx[name][1])
        else:
            assert False
    def get_ram_wire(name, msb, lsb, default="1'b0"):
        wire_bits = []
        for i in range(msb, lsb-1, -1):
Example #5
0
for tile in ic.ramb_tiles:
    for entry in ic.tile_db(tile[0], tile[1]):
        if entry[1] == "RamConfig":
            assert entry[2] not in ram_config_bitidx
            ram_config_bitidx[entry[2]] = ('B', entry[0])
    for entry in ic.tile_db(tile[0], tile[1] + 1):
        if entry[1] == "RamConfig":
            assert entry[2] not in ram_config_bitidx
            ram_config_bitidx[entry[2]] = ('T', entry[0])
    break

for tile in ic.ramb_tiles:
    ramb_config = icebox.tileconfig(ic.tile(tile[0], tile[1]))
    ramt_config = icebox.tileconfig(ic.tile(tile[0], tile[1] + 1))
    if ic.device == "8k":
        negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1"
        negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1] + 1)) == "1"
    else:
        negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1"
        negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1] + 1)) == "1"

    def get_ram_config(name):
        assert name in ram_config_bitidx
        if ram_config_bitidx[name][0] == 'B':
            return ramb_config.match(ram_config_bitidx[name][1])
        elif ram_config_bitidx[name][0] == 'T':
            return ramt_config.match(ram_config_bitidx[name][1])
        else:
            assert False

    def get_ram_wire(name, msb, lsb, default="1'b0"):
Example #6
0
             net_cin)
        ])
    if seq_bits[1] == "1":
        n = next_netname()
        text_wires.append("wire %s;" % n)
        if not strip_comments:
            text_wires.append("// FF %s" % (lut, ))
            text_wires.append("")
        net_cen = seg_to_net((lut[0], lut[1], "lutff_global/cen"), "1'b1")
        net_clk = seg_to_net((lut[0], lut[1], "lutff_global/clk"), "1'b0")
        net_sr = seg_to_net((lut[0], lut[1], "lutff_global/s_r"), "1'b0")
        if seq_bits[3] == "0":
            always_stmts.append(
                "/* FF %2d %2d %2d */ always @(%sedge %s) if (%s) %s <= %s ? 1'b%s : %s;"
                % (lut[0], lut[1], lut[2],
                   "neg" if icebox.get_negclk_bit(tile) == "1" else "pos",
                   net_clk, net_cen, net_out, net_sr, seq_bits[2], n))
        else:
            always_stmts.append(
                "/* FF %2d %2d %2d */ always @(%sedge %s, posedge %s) if (%s) %s <= 1'b%s; else if (%s) %s <= %s;"
                % (lut[0], lut[1], lut[2], "neg"
                   if icebox.get_negclk_bit(tile) == "1" else "pos", net_clk,
                   net_sr, net_sr, net_out, seq_bits[2], net_cen, net_out, n))
        wire_to_reg.add(net_out)
        net_out = n
    if not "1" in lut_bits:
        const_assigns.append([net_out, "1'b0"])
    elif not "0" in lut_bits:
        const_assigns.append([net_out, "1'b1"])
    else: