def __init__(self, platform, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, l2_size=32, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="Arty DMA Test SoC", ident_version=True, reserve_nmi_interrupt=False, **kwargs) self.submodules.crg = CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6)) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True))
def __init__(self, sys_clk_freq=int(100e6), expansion="debug", **kwargs): platform = ztex213.Platform(expansion=expansion) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Ztex 2.13", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125 origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = mimas_a7.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def __init__(self, platform, **kwargs): clk_freq = 50 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.submodules.dna = dna.DNA() # front panel (ATX) self.submodules.front_panel = FrontPanelGPIO(platform, clk_freq) self.comb += self.crg.reset.eq(self.front_panel.reset) # sdram self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") sdram_module = MT41J128M16(self.clk_freq, "1:4") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq)
def __init__(self, variant="ztex2.13a", sys_clk_freq=int(100e6), expansion="debug", with_led_chaser=True, **kwargs): platform = ztex213.Platform(variant=variant, expansion=expansion) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Ztex 2.13", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, uart_name="usb_fifo", **kwargs): platform = mimas_a7.Platform() # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=integrated_rom_size, integrated_sram_size=0x8000, uart_name=uart_name, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings)
def __init__(self, platform, **kwargs): clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="NeTV2 LiteX Base SoC", **kwargs) self.submodules.crg = _CRG(platform) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # sdram bist generator_port = self.sdram.crossbar.get_port(mode="write") self.submodules.generator = LiteDRAMBISTGenerator(generator_port) checker_port = self.sdram.crossbar.get_port(mode="read") self.submodules.checker = LiteDRAMBISTChecker(checker_port)
def __init__(self, platform, **kwargs): kwargs['cpu_type'] = None clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="NeTV2 LiteX Base SoC", with_uart=False, **kwargs) self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), self.clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # sdram bist ddr_generator_port = self.sdram.crossbar.get_port(mode="write") self.submodules.ddr_generator = LiteDRAMBISTGenerator( ddr_generator_port) ddr_checker_port = self.sdram.crossbar.get_port(mode="read") self.submodules.ddr_checker = LiteDRAMBISTChecker(ddr_checker_port) # led blink counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, platform, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__( self, platform, clk_freq, integrated_rom_size=0x5000, integrated_sram_size=0x4000, #shadow_base=0x00000000, ident="NeTV2 LiteX Base SoC", reserve_nmi_interrupt=False, cpu_type="vexriscv", cpu_variant="debug", **kwargs) self.comb += self.uart.reset.eq(self.cpu_or_bridge.debug_reset) self.submodules.crg = CRG(platform) # self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() self.crg.cd_sys.clk.attr.add("keep") platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6)) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # common led self.sys_led = Signal() self.pcie_led = Signal() self.comb += platform.request("fpga_led0", 0).eq( self.sys_led ^ self.pcie_led) #TX0 green self.comb += platform.request("fpga_led1", 0).eq(0) #TX0 red # sys led sys_counter = Signal(32) self.sync += sys_counter.eq(sys_counter + 1) self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): platform = netv2.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=integrated_rom_size, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform, sys_clk_freq) # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
def __init__(self, platform, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="NeTV2 LiteX Base SoC", **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") #self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) # sdram sdram_module = MT41J128M16(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY( platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) controller_settings = ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # common led self.sys_led = Signal() self.pcie_led = Signal() self.comb += platform.request("user_led", 0).eq(self.sys_led ^ self.pcie_led) #checker_port = self.sdram.crossbar.get_port(mode="read") #self.submodules.checker = LiteDRAMBISTChecker(checker_port) # led blink #counter = Signal(32) #self.sync.clk125 += counter.eq(counter + 1) #self.comb += platform.request("user_led", 0).eq(counter[26]) # sys led sys_counter = Signal(32) self.sync += sys_counter.eq(sys_counter + 1) self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, **kwargs): platform = aller.Platform() # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "crossover" # Defaults to Crossover UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Aller", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs): platform = tagus.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tagus", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width=128, bar0_size=0x20000) self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_ethernet=False, **kwargs): platform = mimas_a7.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Mimas A7", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_ethernet(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x4000) sys_clk_freq = 50 * 1000000 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT41J128M16(self.clk_freq, "1:4") self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.add_csr("ddrphy") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] # Basic peripherals ------------------------------------------------------------------------ self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas")
def __init__(self, platform, **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x6000, integrated_sram_size=0x4000, #shadow_base=0x00000000, ident="NeTV2 LiteX Reversing SoC", reserve_nmi_interrupt=False, **kwargs) self.submodules.crg = CRG(platform) self.submodules.dna = dna.DNA() self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6)) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=False)) # common led self.sys_led = Signal() self.pcie_led = Signal() self.comb += platform.request("user_led", 0).eq(self.sys_led ^ self.pcie_led) # sys led sys_counter = Signal(32) self.sync += sys_counter.eq(sys_counter + 1) self.comb += self.sys_led.eq(sys_counter[26])
def __init__(self, platform, **kwargs): clk_freq = 50 * 1000000 if 'expansion' in kwargs: tofe_board_name = kwargs.get('expansion') del kwargs['expansion'] else: tofe_board_name = None SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, with_uart=True, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) # sdram sdram_module = MT41J128M16(self.clk_freq, "1:4") self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ]
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, ident_version=True, with_jtagbone=True, with_mapped_flash=False, **kwargs): platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTech XC7A35T" + (" + Daughterboard" if with_daughterboard else ""), ident_version = ident_version, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # The daughterboard has the tx clock wired to a non-clock pin, so we can't help it self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]") # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # Flash (through LiteSPI, experimental). if with_mapped_flash: self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), MT25QL128(Codes.READ_1_1_1)) self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.cpu.endianness) spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=MT25QL128.total_size, cached=False) self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) if not with_daughterboard and kwargs["uart_name"] == "serial": kwargs["uart_name"] = "jtag_serial"
def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, csr_data_width=32, integrated_rom_size=0x10000, integrated_sram_size=0x10000, integrated_main_ram_size= 0x10000, # FIXME: keep this for initial PCIe tests ident="Tagus LiteX Test SoC", ident_version=True, with_uart=not with_pcie_uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") platform.add_platform_command( "create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.msis = { "DMA_WRITER": self.pcie_dma.writer.irq, "DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.msis.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # pcie_uart if with_pcie_uart: class PCIeUART(Module, AutoCSR): def __init__(self, uart): self.rx_valid = CSRStatus() self.rx_ready = CSR() self.rx_data = CSRStatus(8) self.tx_valid = CSR() self.tx_ready = CSRStatus() self.tx_data = CSRStorage(8) # # # # cpu to pcie self.comb += [ self.rx_valid.status.eq(uart.sink.valid), uart.sink.ready.eq(self.rx_ready.re), self.rx_data.status.eq(uart.sink.data), ] # pcie to cpu self.sync += [ If(self.tx_valid.re, uart.source.valid.eq(1)).Elif( uart.source.ready, uart.source.valid.eq(0)) ] self.comb += [ self.tx_ready.status.eq(~uart.source.valid), uart.source.data.eq(self.tx_data.storage) ] uart_interface = RS232PHYInterface() self.submodules.uart = UART(uart_interface) self.add_csr("uart") self.add_interrupt("uart") self.submodules.pcie_uart = PCIeUART(uart_interface) self.add_csr("pcie_uart") # Leds ------------------------------------------------------------------------------------- # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) self.comb += [ platform.request("user_led", 0).eq(1), platform.request("user_led", 1).eq(sys_counter[26]), platform.request("user_led", 2).eq(1), ]
def __init__(self, platform, with_pcie=False, **kwargs): sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Tagus", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width = 64, bar0_size = 0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, base_address = self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) self.add_csr("pcie_dma0") self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, variant, version, sys_clk_freq, trng, usb, sdram, engine, i2c, bw2, cg3, cg6, cg3_res, sdcard, **kwargs): framebuffer = (bw2 or cg3 or cg6) print(f"Building SBusFPGA for board version {version}") kwargs["cpu_type"] = "None" kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False kwargs["with_timer"] = False self.sys_clk_freq = sys_clk_freq self.platform = platform = ztex213_sbus.Platform(variant=variant, version=version) if (framebuffer and (version == "V1.2")): platform.add_extension(ztex213_sbus._vga_pmod_io_v1_2) if (framebuffer): hres = int(cg3_res.split("@")[0].split("x")[0]) vres = int(cg3_res.split("@")[0].split("x")[1]) if (bw2): cg3_fb_size = bw2_fb.bw2_rounded_size(hres, vres) else: cg3_fb_size = cg3_fb.cg3_rounded_size(hres, vres) print( f"Reserving {cg3_fb_size} bytes ({cg3_fb_size//1048576} MiB) for the CG3/CG6" ) else: hres = 0 vres = 0 cg3_fb_size = 0 litex.soc.cores.video.video_timings.update(cg3_fb.cg3_timings) # if there's just one DVMA bus master in the design, # then we'll connect it directly to the wishbone interface # in the FSM rather than to the system Wishbone bus # sdcard has two by itself, so never a single_dvma_master single_dvma_master = False if (usb and not engine and not sdcard): # fixme: others? single_dvma_master = True if (engine and not usb and not sdcard): # fixme: others? single_dvma_master = True SoCCore.__init__( self, platform=platform, sys_clk_freq=sys_clk_freq, clk_freq=sys_clk_freq, csr_paging=0x1000, # default is 0x800 **kwargs) # *** This mem-map is also exposed in the FSM (matched prefixes) *** # and in the PROM (to tell NetBSD where everything is) # Currently it is a straight mapping between the two: # the physical address here are used as offset in the SBus # reserved area of 256 MiB # Anything at 0x10000000 is therefore unreachable directly # The position of the 'dvma_bridge' is so it overlaps # the virtual address space used by NetBSD DMA allocators # (themselves constrained by the SBus MMU capabilities) self.wb_mem_map = wb_mem_map = { "prom": 0x00000000, # 256 Kib ought to be enough for anybody (we're using < 8 Kib now...) "csr": 0x00040000, "usb_host": 0x00080000, # OHCI registers are here, not in CSR #"usb_shared_mem": 0x00090000, # unused ATM "curve25519engine": 0x000a0000, # includes microcode (4 KiB@0) and registers (16 KiB @ 64 KiB) "cg6_bt": 0x00200000, # required for compatibility, bt_regs for cg6 #"cg6_dhc": 0x00240000, # required for compatibility, unused "cg6_alt": 0x00280000, # required for compatibility "cg6_fhc": 0x00300000, # required for compatibility #"cg6_thc": 0x00301000, # required for compatibility "cg3_bt": 0x00400000, # required for compatibility, bt_regs for cg3 & bw2 "cg6_accel_rom": 0x00410000, # R5 microcode "cg6_accel_ram": 0x00420000, # R5 microcode working space (stack) "cg6_fbc": 0x00700000, # required for compatibility #"cg6_tec": 0x00701000, # required for compatibility "cg3_pixels": 0x00800000, # required for compatibility, 1/2/4/8 MiB for now (up to 0x00FFFFFF inclusive) (bw2, cg3 and cg6 idem) "main_ram": 0x80000000, # not directly reachable from SBus mapping (only 0x0 - 0x10000000 is accessible), "video_framebuffer": 0x80000000 + 0x10000000 - cg3_fb_size, # Updated later "dvma_bridge": 0xfc000000, # required to match DVMA virtual addresses } self.mem_map.update(wb_mem_map) self.submodules.crg = _CRG( platform=platform, sys_clk_freq=sys_clk_freq, usb=usb, usb_clk_freq=48e6, engine=engine, framebuffer=framebuffer, pix_clk=litex.soc.cores.video.video_timings[cg3_res]["pix_clk"]) #self.platform.add_period_constraint(self.platform.lookup_request("SBUS_3V3_CLK", loose=True), 1e9/25e6) # SBus max ## add our custom timings after the clocks have been defined xdc_timings_filename = None if (version == "V1.0"): xdc_timings_filename = "/home/dolbeau/SBusFPGA/sbus-to-ztex-gateware/sbus-to-ztex-timings.xdc" self.platform.add_extension(ztex213_sbus._usb_io_v1_0) elif (version == "V1.2"): xdc_timings_filename = "/home/dolbeau/SBusFPGA/sbus-to-ztex-gateware/sbus-to-ztex-timings-V1_2.xdc" if (xdc_timings_filename != None): xdc_timings_file = open(xdc_timings_filename) xdc_timings_lines = xdc_timings_file.readlines() for line in xdc_timings_lines: if (line[0:3] == "set"): fix_line = line.strip().replace("{", "{{").replace("}", "}}") #print(fix_line) platform.add_platform_command(fix_line) if (version == "V1.0"): self.submodules.leds = LedChaser( pads=platform.request("SBUS_DATA_OE_LED_2"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") if (usb): self.add_usb_host_custom(pads=platform.request("usb"), usb_clk_freq=48e6, single_dvma_master=single_dvma_master) pad_usb_interrupt = platform.get_irq(irq_req=3, device="usb_host", next_down=True, next_up=False) if (pad_usb_interrupt is None): print(" ***** ERROR ***** USB requires an interrupt") assert (False) sig_usb_interrupt = Signal(reset=1) # the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt) self.comb += pad_usb_interrupt.eq(sig_usb_interrupt) self.comb += sig_usb_interrupt.eq(~self.usb_host.interrupt) ## #pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED") #SBUS_DATA_OE_LED_o = Signal() #self.comb += pad_SBUS_DATA_OE_LED.eq(SBUS_DATA_OE_LED_o) #pad_SBUS_DATA_OE_LED_2 = platform.request("SBUS_DATA_OE_LED_2") #SBUS_DATA_OE_LED_2_o = Signal() #self.comb += pad_SBUS_DATA_OE_LED_2.eq(SBUS_DATA_OE_LED_2_o) #self.comb += SBUS_DATA_OE_LED_o.eq(~SBUS_3V3_INT1s_o) prom_file = "prom_{}.fc".format(version.replace(".", "_")) #prom_file = "SUNW,501-2325.bin" # real TGX #prom_file = "SUNW,501-1415.bin" # real cg3 #prom_file = "SUNW,501-2253.bin" # real TGX+ prom_data = soc_core.get_mem_data(prom_file, "big") # prom = Array(prom_data) #print("\n****************************************\n") #for i in range(len(prom)): # print(hex(prom[i])) #print("\n****************************************\n") self.add_ram( "prom", origin=self.mem_map["prom"], size=2**15, contents=prom_data, mode="r" ) ### FIXME: round up the prom_data size & check for <= 2**16! #getattr(self,"prom").mem.init = prom_data #getattr(self,"prom").mem.depth = 2**15 self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram( "sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size=0, ) avail_sdram = self.bus.regions["main_ram"].size ###from sdram_init import DDR3FBInit ###self.submodules.sdram_init = DDR3FBInit(sys_clk_freq=sys_clk_freq, bitslip=1, delay=25) ###self.bus.add_master(name="DDR3Init", master=self.sdram_init.bus) base_fb = self.wb_mem_map[ "main_ram"] + avail_sdram - 1048576 # placeholder if (framebuffer): if (avail_sdram >= cg3_fb_size): avail_sdram = avail_sdram - cg3_fb_size base_fb = self.wb_mem_map["main_ram"] + avail_sdram self.wb_mem_map["video_framebuffer"] = base_fb else: print( "***** ERROR ***** Can't have a FrameBuffer without main ram\n" ) assert (False) # don't enable anything on the SBus side for 20 seconds after power up # this avoids FPGA initialization messing with the cold boot process # requires us to reset the SPARCstation afterward so the FPGA board # is properly identified - or to 'probe-slot' # This is in the 'native' ClockDomain that is never reset hold_reset_ctr = Signal(30, reset=960000000) self.sync.native += If(hold_reset_ctr > 0, hold_reset_ctr.eq(hold_reset_ctr - 1)) hold_reset = Signal(reset=1) self.comb += hold_reset.eq(~(hold_reset_ctr == 0)) # Interface SBus to wishbone # we need to cross clock domains wishbone_slave_sbus = wishbone.Interface( data_width=self.bus.data_width) wishbone_master_sys = wishbone.Interface( data_width=self.bus.data_width) self.submodules.wishbone_master_sbus = WishboneDomainCrossingMaster( platform=self.platform, slave=wishbone_master_sys, cd_master="sbus", cd_slave="sys") self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster( platform=self.platform, slave=wishbone_slave_sbus, cd_master="sys", cd_slave="sbus") # SPARCstation 20 slave interface to the main memory are limited to 32-bytes burst (32-bits wide, 8 word long) # burst_size=16 should work on Ultra systems, but then they probably should go for 64-bits ET as well... # Older systems are probably limited to burst_size=4, (it should always be available) burst_size = 8 data_width = burst_size * 4 data_width_bits = burst_size * 32 blk_addr_width = 32 - log2_int(data_width) self.tosbus_layout = [ ("address", 32), ("data", data_width_bits), ] self.fromsbus_layout = [ ("blkaddress", blk_addr_width), ("data", data_width_bits), ] self.fromsbus_req_layout = [ ("blkaddress", blk_addr_width), ("dmaaddress", 32), ] self.submodules.tosbus_fifo = ClockDomainsRenamer({ "read": "sbus", "write": "sys" })(AsyncFIFOBuffered(width=layout_len(self.tosbus_layout), depth=burst_size)) self.submodules.fromsbus_fifo = ClockDomainsRenamer({ "write": "sbus", "read": "sys" })(AsyncFIFOBuffered(width=layout_len(self.fromsbus_layout), depth=burst_size)) self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({ "read": "sbus", "write": "sys" })(AsyncFIFOBuffered(width=layout_len(self.fromsbus_req_layout), depth=burst_size)) if (sdram): self.submodules.dram_dma_writer = LiteDRAMDMAWriter( port=self.sdram.crossbar.get_port(mode="write", data_width=data_width_bits), fifo_depth=4, fifo_buffered=True) self.submodules.dram_dma_reader = LiteDRAMDMAReader( port=self.sdram.crossbar.get_port(mode="read", data_width=data_width_bits), fifo_depth=4, fifo_buffered=True) self.submodules.exchange_with_mem = ExchangeWithMem( soc=self, platform=platform, tosbus_fifo=self.tosbus_fifo, fromsbus_fifo=self.fromsbus_fifo, fromsbus_req_fifo=self.fromsbus_req_fifo, dram_dma_writer=self.dram_dma_writer, dram_dma_reader=self.dram_dma_reader, mem_size=avail_sdram // 1048576, burst_size=burst_size, do_checksum=False) pad_sdram_interrupt = platform.get_irq(irq_req=4, device="sdram", next_down=True, next_up=False) if (pad_sdram_interrupt is None): print(" ***** ERROR ***** sdram requires an interrupt") assert (False) sig_sdram_interrupt = Signal(reset=1) # the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt) self.comb += pad_sdram_interrupt.eq(sig_sdram_interrupt) self.comb += sig_sdram_interrupt.eq( ~self.exchange_with_mem.irq) ## _sbus_bus = SBusFPGABus(soc=self, platform=self.platform, hold_reset=hold_reset, wishbone_slave=wishbone_slave_sbus, wishbone_master=self.wishbone_master_sbus, tosbus_fifo=self.tosbus_fifo, fromsbus_fifo=self.fromsbus_fifo, fromsbus_req_fifo=self.fromsbus_req_fifo, version=version, burst_size=burst_size, cg3_fb_size=cg3_fb_size, cg3_base=base_fb) #self.submodules.sbus_bus = _sbus_bus self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus) self.submodules.sbus_bus_stat = SBusFPGABusStat(soc=self, sbus_bus=self.sbus_bus) self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys) if (usb): if (single_dvma_master): self.comb += self.usb_host.wb_dma.connect( self.wishbone_slave_sys) if (sdcard): self.add_sdcard() #pad_sdcard_interrupt = platform.get_irq(irq_req=2, device="sdcard", next_down=True, next_up=False) #if (pad_sdcard_interrupt is None): # print(" ***** ERROR ***** sdcard requires an interrupt") # assert(False) #sig_sdcard_interrupt = Signal(reset=1) ## the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt) #self.comb += pad_sdcard_interrupt.eq(sig_sdcard_interrupt) #self.comb += sig_sdcard_interrupt.eq(~self.sdirq.irq) ## if (usb or engine or sdcard): if (not single_dvma_master): self.bus.add_slave(name="dvma_bridge", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get( "dvma_bridge", None), size=0x03ffffff, cached=False)) if (trng): self.submodules.trng = NeoRV32TrngWrapper(platform=platform) # beware the naming, as 'clk50' 'sysclk' 'clk200' are used in the original platform constraints # the local engine.py was slightly modified to have configurable names, so we can have 'clk50', 'clk100', 'clk200' # Beware that Engine implicitely runs in 'sys' by default, need to rename that one as well # Actually renaming 'sys' doesn't work - unless we can CDC the CSRs as well if (engine): self.submodules.curve25519engine = ClockDomainsRenamer({ "eng_clk": "clk50", "rf_clk": "clk200", "mul_clk": "clk100_gated" })(Engine(platform=platform, prefix=self.mem_map.get("curve25519engine", None))) # , "sys":"clk100" self.bus.add_slave( "curve25519engine", self.curve25519engine.bus, SoCRegion(origin=self.mem_map.get("curve25519engine", None), size=0x20000, cached=False)) if (not single_dvma_master): self.bus.add_master(name="curve25519engineLS", master=self.curve25519engine.busls) else: self.comb += self.curve25519engine.busls.connect( self.wishbone_slave_sys) self.comb += self.crg.curve25519_on.eq( self.curve25519engine.power.fields.on) if (i2c): self.submodules.i2c = i2c.RTLI2C(platform, pads=platform.request("i2c")) if (framebuffer): self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if (bw2): self.submodules.bw2 = bw2_fb.bw2( soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga" ) # clock_domain for the VGA side, bw2 is running in cd_sys self.bus.add_slave("bw2_bt", self.bw2.bus, SoCRegion(origin=self.mem_map.get( "cg3_bt", None), size=0x1000, cached=False)) # bw2 uses cg3_bt elif (cg3): self.submodules.cg3 = cg3_fb.cg3( soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga" ) # clock_domain for the VGA side, cg3 is running in cd_sys self.bus.add_slave( "cg3_bt", self.cg3.bus, SoCRegion(origin=self.mem_map.get("cg3_bt", None), size=0x1000, cached=False)) else: self.submodules.cg6 = cg6_fb.cg6( soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga" ) # clock_domain for the VGA side, cg6 is running in cd_sys self.bus.add_slave( "cg6_bt", self.cg6.bus, SoCRegion(origin=self.mem_map.get("cg6_bt", None), size=0x1000, cached=False)) if (cg6): self.submodules.cg6_accel = cg6_accel.CG6Accel(soc=self, base_fb=base_fb, hres=hres, vres=vres) self.bus.add_slave( "cg6_fbc", self.cg6_accel.bus, SoCRegion(origin=self.mem_map.get("cg6_fbc", None), size=0x2000, cached=False)) self.bus.add_slave( "cg6_fhc", self.cg6.bus2, SoCRegion(origin=self.mem_map.get("cg6_fhc", None), size=0x2000, cached=False)) self.bus.add_slave( "cg6_alt", self.cg6.bus3, SoCRegion(origin=self.mem_map.get("cg6_alt", None), size=0x2000, cached=False)) self.bus.add_master(name="cg6_accel_r5_i", master=self.cg6_accel.ibus) self.bus.add_master(name="cg6_accel_r5_d", master=self.cg6_accel.dbus) cg6_rom_file = "blit.raw" cg6_rom_data = soc_core.get_mem_data(cg6_rom_file, "little") self.add_ram("cg6_accel_rom", origin=self.mem_map["cg6_accel_rom"], size=2**13, contents=cg6_rom_data, mode="r") self.add_ram("cg6_accel_ram", origin=self.mem_map["cg6_accel_ram"], size=2**12, mode="rw") print("IRQ to Device map:\n") print(platform.irq_device_map) print("Device to IRQ map:\n") print(platform.device_irq_map) #disable remaining IRQs if (version == "V1.0"): platform.avail_irqs.add(7) for irq in platform.avail_irqs: pad_int = platform.request(f"SBUS_3V3_INT{irq}s") oe_int = Signal(reset=0) val_int = Signal(reset=1) self.specials += Tristate(pad_int, val_int, oe_int, None)
def __init__(self, platform, **kwargs): clk_freq = 50 * 1000000 if 'tofe_board' in kwargs: tofe_board_name = kwargs.get('tofe_board') del kwargs['tofe_board'] else: tofe_board_name = None SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x4000, with_uart=False, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) self.submodules.info = info.Info(platform, "opsis", self.__class__.__name__[:8]) self.submodules.opsis_i2c = opsis_i2c.OpsisI2C(platform) self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200) self.suart.add_uart_pads(platform.request('fx2_serial')) self.submodules.uart = self.suart.uart self.submodules.spiflash = spi_flash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div) self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size # front panel (ATX) self.submodules.front_panel = FrontPanelGPIO(platform, clk_freq) self.comb += self.crg.reset.eq(self.front_panel.reset) # sdram sdram_module = MT41J128M16(self.clk_freq, "1:4") self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip=0, wr_bitslip=4, dqs_ddr_alignment="C0") controller_settings = ControllerSettings(with_bandwidth=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] if tofe_board_name: if tofe_board_name == 'lowspeedio': self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)( platform, self.suart) else: self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)( platform)
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, with_jtagbone=True, with_spi_flash=False, **kwargs): platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard) # SoCCore ---------------------------------------------------------------------------------- if (kwargs["uart_name"] == "serial") and (not with_daughterboard): kwargs["uart_name"] = "gpio_serial" SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTech XC7A35T" + (" + Daughterboard" if with_daughterboard else ""), **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # The daughterboard has the tx clock wired to a non-clock pin, so we can't help it self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]") # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import MT25QL128 from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=MT25QL128(Codes.READ_1_1_1), with_master=True) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) if not with_daughterboard and kwargs["uart_name"] == "serial": kwargs["uart_name"] = "jtag_serial"
def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tagus", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.msis = { "DMA_WRITER": self.pcie_dma.writer.irq, "DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.msis.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, **kwargs): if kwargs.get('cpu_type', None) == "mor1kx": dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) sys_clk_freq = 50*1000000 if 'expansion' in kwargs: tofe_board_name = kwargs.get('expansion') del kwargs['expansion'] else: tofe_board_name = None # disable uart kwargs['with_uart'] = False # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) # Add specialized uart --------------------------------------------------------------------- self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200) self.suart.add_uart_pads(platform.request('fx2_serial')) self.submodules.uart = self.suart.uart self.add_csr("uart") self.add_interrupt("uart") # DDR3 SDRAM ------------------------------------------------------------------------------- if True: sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY( platform.request("ddram"), rd_bitslip = 0, wr_bitslip = 4, dqs_ddr_alignment="C0") self.add_csr("ddrphy") controller_settings = ControllerSettings( with_bandwidth=True) self.register_sdram( self.ddrphy, geom_settings = sdram_module.geom_settings, timing_settings = sdram_module.timing_settings, controller_settings=controller_settings) self.comb += [ self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb), self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb), ] # Basic peripherals ------------------------------------------------------------------------ # info module self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") # control and status module #self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas") # opsis specific i2c module self.submodules.opsis_i2c = opsis_i2c.OpsisI2C(platform) self.add_csr("opsis_i2c") # front panel (ATX) module self.submodules.front_panel = FrontPanelGPIO(platform, sys_clk_freq) self.comb += self.crg.reset.eq(self.front_panel.reset) self.add_csr("front_panel") # Expansion boards ------------------------------------------------------------------------- if tofe_board_name: if tofe_board_name == 'lowspeedio': self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)(platform, self.suart) else: self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)(platform) # Add debug interface if the CPU has one --------------------------------------------------- if hasattr(self.cpu, "debug_bus"): self.register_mem( name="vexriscv_debug", address=0xf00f0000, interface=self.cpu.debug_bus, size=0x100) # Memory mapped SPI Flash ------------------------------------------------------------------ self.submodules.spiflash = spi_flash.SpiFlash( platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div, endianness=self.cpu.endianness) self.add_csr("spiflash") self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size) self.add_wb_slave( self.mem_map["spiflash"], self.spiflash.bus, platform.spiflash_total_size) self.add_memory_region( "spiflash", self.mem_map["spiflash"], platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size define_flash_constants(self)
def __init__(self, platform, with_sdram=True, with_ethernet=False, with_etherbone=True, with_sdcard=True, with_pcie=False, with_hdmi_in0=False, with_hdmi_out0=False, with_hdmi_in1=False, with_hdmi_out1=False, with_interboard_communication=False): assert not (with_pcie and with_interboard_communication) sys_clk_freq = int(100e6) sd_freq = int(100e6) SoCSDRAM.__init__(self, platform, sys_clk_freq, #cpu_type="vexriscv", l2_size=32, cpu_type=None, l2_size=32, #csr_data_width=8, csr_address_width=14, csr_data_width=32, csr_address_width=14, integrated_rom_size=0x8000, integrated_sram_size=0x4000, integrated_main_ram_size=0x8000 if not with_sdram else 0, ident="NeTV2 LiteX Test SoC", ident_version=True, reserve_nmi_interrupt=False) # crg self.submodules.crg = CRG(platform, sys_clk_freq) # dnax self.submodules.dna = dna.DNA() # xadc self.submodules.xadc = xadc.XADC() # icap self.submodules.icap = ICAP(platform) # flash self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6)) # sdram if with_sdram: self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # ethernet if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # etherbone if with_etherbone: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq) self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")) self.add_wb_master(self.cpu.wishbone.bus) #self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") #self.add_wb_master(self.etherbone.wishbone.bus) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # sdcard self.submodules.sdclk = SDClockerS7() self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq) self.crg.cd_sys.clk.attr.add("keep") self.sdclk.cd_sd.clk.attr.add("keep") self.sdclk.cd_sd_fb.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.sdclk.cd_sd.clk, self.sdclk.cd_sd_fb.clk) # pcie if with_pcie: # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2")) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000) self.add_wb_master(self.pcie_bridge.wishbone) # pcie dma self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # interboard communication if with_interboard_communication: self.clock_domains.cd_refclk = ClockDomain() self.submodules.refclk_pll = refclk_pll = S7PLL() refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6) refclk_pll.create_clkout(self.cd_refclk, 125e6) platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # qpll qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9) print(qpll) self.submodules += qpll # gtp gtp = GTP(qpll, platform.request("interboard_comm_tx"), platform.request("interboard_comm_rx"), sys_clk_freq, clock_aligner=True, internal_loopback=False) self.submodules += gtp counter = Signal(32) self.sync.tx += counter.eq(counter + 1) # send counter to other-board self.comb += [ gtp.encoder.k[0].eq(1), gtp.encoder.d[0].eq((5 << 5) | 28), gtp.encoder.k[1].eq(0), gtp.encoder.d[1].eq(counter[26:]) ] # receive counter and display it on leds self.comb += [ platform.request("user_led", 3).eq(gtp.rx_ready), platform.request("user_led", 4).eq(gtp.decoders[1].d[0]), platform.request("user_led", 5).eq(gtp.decoders[1].d[1]) ] gtp.cd_tx.clk.attr.add("keep") gtp.cd_rx.clk.attr.add("keep") platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk) # hdmi in 0 if with_hdmi_in0: hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk), for clk in [self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6)) # hdmi out 0 if with_hdmi_out0: hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut( platform.device, platform.request("hdmi_out", 0), hdmi_out0_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # hdmi in 1 if with_hdmi_in1: hdmi_in1_pads = platform.request("hdmi_in", 1) self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in1 = HDMIIn( hdmi_in1_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk), for clk in [self.hdmi_in1.clocking.cd_pix.clk, self.hdmi_in1.clocking.cd_pix1p25x.clk, self.hdmi_in1.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6)) # hdmi out 1 if with_hdmi_out1: hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True) self.submodules.hdmi_out1 = VideoOut( platform.device, platform.request("hdmi_out", 1), hdmi_out1_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk, self.hdmi_out1.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) self.comb += platform.request("user_led", 0).eq(sys_counter[26]) # led blinking (pcie) if with_pcie: pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += platform.request("user_led", 1).eq(pcie_counter[26]) # led blinking (sdcard) if with_sdcard: sd_counter = Signal(32) self.sync.sd += sd_counter.eq(sd_counter + 1) self.comb += platform.request("user_led", 1).eq(sd_counter[26])