def do_llvm_target(): print(" Testing module llvm.target") from llvm import target target.initialize_all() target.print_registered_targets() target.get_host_cpu_name() target.get_default_triple() tm = TargetMachine.new() tm = TargetMachine.lookup("arm") tm = TargetMachine.arm() tm = TargetMachine.thumb() tm = TargetMachine.x86() tm = TargetMachine.x86_64() tm.target_data tm.target_name tm.target_short_description tm.triple tm.cpu tm.feature_string tm.target if llvm.version >= (3, 4): tm.reg_info tm.subtarget_info tm.asm_info tm.instr_info tm.instr_analysis tm.disassembler tm.is_little_endian()
def do_llvm_mc(): if llvm.version < (3, 4): return from llvm import target from llvm import mc target.initialize_all() tm = TargetMachine.x86() dasm = mc.Disassembler(tm) for (offset, data, instr) in dasm.decode("c3", 0): pass
from . import grammar from . import ast from . import mutation from . import typesys from . import sourcegen from . import log try: from llvm import ee from llvm import passes from llvm import target import ctypes from . import codegen from . import fn target.initialize_all() except ImportError: print('Cannot find llvmpy, code generation will not function') pass class PrintVisitor(ast.NodeVisitor): def __init__(self): self.level = 0 def visit_VarDeclListNode(self, node, arg=None): ast.NodeVisitor.default_visit(self, node) def visit_StatementListNode(self, node, arg=None): ast.NodeVisitor.default_visit(self, node)
import os from fractions import Fraction from llvm import core as lc from llvm import target as lt from artiq.py2llvm import base_types from artiq.language import units lt.initialize_all() _syscalls = { "rpc": "i+:i", "gpio_set": "ib:n", "rtio_oe": "ib:n", "rtio_set": "Iii:n", "rtio_get_counter": "n:I", "rtio_get": "iI:I", "rtio_pileup_count": "i:i", "dds_phase_clear_en": "ib:n", "dds_program": "IiiiIbb:n", } _chr_to_type = { "n": lambda: lc.Type.void(), "b": lambda: lc.Type.int(1), "i": lambda: lc.Type.int(32), "I": lambda: lc.Type.int(64) }