def tristate():
from myhdl import TristateSignal
clk = Signal(bool(0))
x = TristateSignal(True) # single bit
y = TristateSignal(intbv(0)) # intbv with undefined width
z = TristateSignal(intbv(0)[8:]) # intbv with fixed width
inst = genTristate(clk, x, y, z)
return inst
def bench(self, obuf=None):
if obuf:
toVerilog(tristate_obuf_i, obuf)
A, Y, OE = obuf.interface()
inst = setupCosimulation(name='tristate_obuf_i',
**toVerilog.portmap)
else:
Y = TristateSignal(True)
A = Signal(True)
OE = Signal(False)
toVerilog(tristate_obuf, A, Y, OE)
inst = setupCosimulation(name='tristate_obuf', **toVerilog.portmap)
# inst = tristate_obuf(A, Y, OE)
@instance
def stimulus():
yield delay(1)
# print now(), A, OE, Y
self.assertEqual(Y, None)
OE.next = True
yield delay(1)
# print now(), A, OE, Y
self.assertEqual(Y, A)
A.next = not A
yield delay(1)
# print now(), A, OE, Y
self.assertEqual(Y, A)
OE.next = False
yield delay(1)
# print now(), A, OE, Y
self.assertEqual(Y, None)
raise StopSimulation
return instances()
iostandard='LVTTL'),
'cclk':
dict(pins=(70, ), iostandard='LVTTL'),
'spi_mosi':
dict(pins=(44, ), iostandard='LVTTL'),
'spi_miso':
dict(pins=(45, ), iostandard='LVTTL'),
'spi_ss':
dict(pins=(48, ), iostandard='LVTTL'),
'spi_sck':
dict(pins=(43, ), iostandard='LVTTL'),
'spi_channel':
dict(pins=(
46,
61,
62,
65,
),
sigtype=TristateSignal(intbv(0)[4:]),
iostandard='LVTTL'),
'avr_tx':
dict(pins=(55, ), iostandard='LVTTL'),
'avr_rx':
dict(pins=(59, ), iostandard='LVTTL'),
'avr_tx_busy':
dict(pins=(39, ), iostandard='LVTTL'),
}
def get_flow(self, top=None):
return ISE(brd=self, top=top)
# the default port map
# @todo: should be able to extact this from the board
# @todo: definition:
# @todo: portmap = brd.map_ports(de0nano_converters)
de0nano_converters.portmap = {
'clock': Clock(0, frequency=50e6),
'reset': Reset(0, active=0, async=True),
'led': Signal(intbv(0)[8:]),
'adc_cs_n': Signal(bool(1)),
'adc_saddr': Signal(bool(1)),
'adc_sdat': Signal(bool(1)),
'adc_sclk': Signal(bool(1)),
'i2c_sclk': Signal(bool(1)),
'i2c_sdat': TristateSignal(bool(0)),
'g_sensor_cs_n': Signal(bool(1)),
'g_sensor_int': Signal(bool(1)),
'lcd_on': Signal(bool(1)),
'lcd_resetn': Signal(bool(1)),
'lcd_csn': Signal(bool(1)),
'lcd_rs': Signal(bool(1)),
'lcd_wrn': Signal(bool(1)),
'lcd_rdn': Signal(bool(1)),
'lcd_data': Signal(intbv(0)[16:])
}
def build():
global brd, flow
brd = get_board('de0nano')
def __init__(self, num_banks=4, addr_width=12, data_width=16, ver='sdr'):
# signals in the interface
self.frequency = 0. # @todo:
self.clk = Signal(bool(0)) # interface clock
self.cke = Signal(bool(0)) # clock enable
self.cs = Signal(bool(0)) # chip select
self.cas = Signal(bool(0)) # column address strobe
self.ras = Signal(bool(0)) # row address strobe
self.we = Signal(bool(0)) # write strobe
self.bs = Signal(intbv(0)[2:]) # bank select
self.addr = Signal(intbv(0)[addr_width:])
self.dqm = Signal(bool(0))
self.dqml = Signal(bool(0))
self.dqmh = Signal(bool(0))
self.dq = TristateSignal(intbv(0)[data_width:])
# the controller and SDRAM bi-dir bus drivers
self.dqo = self.dq.driver()
self.dqi = self.dq.driver()
# the following separate write and read buses are
# not used in an actual device. They are used by
# the model for debug and testing.
self.wdq = Signal(intbv(0)[data_width:])
self.rdq = Signal(intbv(0)[data_width:])
# configurations for the SDRAM interfacing with
self.num_banks = num_banks
self.addr_width = addr_width
self.data_width = data_width
self.ver = ver
# saved read, transactors save the read data here
self.read_data = None
# generic commands for a DRAM, override these for specific (S)DRAM devices
# @todo: attribute of the interface or global definition?
self.Commands = enum(
"NOP", # no operation, ignore all inputs
"ACT", # activate a row in a particular bank
"RD", # read, initiate a read burst to an active row
"WR", # write, initial a write burst to an active row
"PRE", # precharge, close a row in a particular bank
"REF", # refresh, start a refresh operation
# extended commands (???)
"LMR", # load mode register
)
# extract the default timing parameters, all parameters in ns
# but convert to "ps" like ticks.
cycles = {}
for k, v in self.timing.items():
cycles[k] = (v * (self.clock_frequency / 1e9))
# @todo: if 'ddr' in self.ver: cycles[k] *= 2
# add the cycle numbers to the
for k, v in cycles.items():
# majority of the timing parameters are maximum times,
# floor error on the side of margin ...
self.__dict__['cyc_'+k] = int(floor(v))
# convert the time parameters to simulation ticks
# @todo: where to get the global simulation step?
for k, v in self.timing.items():
self.__dict__['tick_'+k] = int(ceil(v * 1000))
class SDRAMInterface(object):
clock_frequency = 100e6
timing = { # all timing parameters in ns
'init': 200000.0, # min init interval
'ras': 45.0, # min interval between active precharge commands
'rcd': 20.0, # min interval between active R/W commands
'ref': 64000000.0, # max refresh interval
'rfc': 65.0, # refresh operaiton duration
'rp': 20.0, # min precharge command duration
'xsr': 75.0, # exit self-refresh time
'wr': 55.0, # @todo ...
}
addr_width = 12 # SDRAM address width
data_width = 16 # SDRAM data width
def __init__(self, num_banks=4, addr_width=12, data_width=16, ver='sdr'):
# signals in the interface
self.frequency = 0. # @todo:
self.clk = Signal(bool(0)) # interface clock
self.cke = Signal(bool(0)) # clock enable
self.cs = Signal(bool(0)) # chip select
self.cas = Signal(bool(0)) # column address strobe
self.ras = Signal(bool(0)) # row address strobe
self.we = Signal(bool(0)) # write strobe
self.bs = Signal(intbv(0)[2:]) # bank select
self.addr = Signal(intbv(0)[addr_width:])
self.dqm = Signal(bool(0))
self.dqml = Signal(bool(0))
self.dqmh = Signal(bool(0))
self.dq = TristateSignal(intbv(0)[data_width:])
# the controller and SDRAM bi-dir bus drivers
self.dqo = self.dq.driver()
self.dqi = self.dq.driver()
# the following separate write and read buses are
# not used in an actual device. They are used by
# the model for debug and testing.
self.wdq = Signal(intbv(0)[data_width:])
self.rdq = Signal(intbv(0)[data_width:])
# configurations for the SDRAM interfacing with
self.num_banks = num_banks
self.addr_width = addr_width
self.data_width = data_width
self.ver = ver
# saved read, transactors save the read data here
self.read_data = None
# generic commands for a DRAM, override these for specific (S)DRAM devices
# @todo: attribute of the interface or global definition?
self.Commands = enum(
"NOP", # no operation, ignore all inputs
"ACT", # activate a row in a particular bank
"RD", # read, initiate a read burst to an active row
"WR", # write, initial a write burst to an active row
"PRE", # precharge, close a row in a particular bank
"REF", # refresh, start a refresh operation
# extended commands (???)
"LMR", # load mode register
)
# extract the default timing parameters, all parameters in ns
# but convert to "ps" like ticks.
cycles = {}
for k, v in self.timing.items():
cycles[k] = (v * (self.clock_frequency / 1e9))
# @todo: if 'ddr' in self.ver: cycles[k] *= 2
# add the cycle numbers to the
for k, v in cycles.items():
# majority of the timing parameters are maximum times,
# floor error on the side of margin ...
self.__dict__['cyc_'+k] = int(floor(v))
# convert the time parameters to simulation ticks
# @todo: where to get the global simulation step?
for k, v in self.timing.items():
self.__dict__['tick_'+k] = int(ceil(v * 1000))
def get_data_driver(self, dir='o'):
if dir == 'o':
drv = self.dqo
else:
drv = self.dqi
return drv
def get_command(self):
""" extract the current command from based in the interface signals
Command table
cs ras cas we dqm
H X X X X : NOP (command inhibit)
L H H H X : NOP
L H H L X : (burst term)
L H L H X : RD
L H L L X : WR
L L H H X : ACT
L L H L X : PRE
L L L H X : REF (auto refresh)
L L L L X : LRM (load mode register)
:return:
"""
cs, ras, cas, we, dqm = (self.cs, self.ras, self.cas,
self.we, self.dqm)
cmd = self.Commands.NOP
if not cs:
if ras and not cas and we:
cmd = self.Commands.RD
elif ras and not cas and not we:
cmd = self.Commands.WR
elif not ras and cas and we:
cmd = self.Commands.ACT
elif not ras and cas and not we:
cmd = self.Commands.PRE
elif not ras and not cas and we:
cmd = self.Commands.REF
elif not ras and not cas and not we:
cmd = self.Commands.LRM
return cmd
def _set_cmd(self, cmd):
pass
def _nop(self):
self.cs.next = False
self.ras.next = True
self.cas.next = True
self.we.next = True
yield self.clk.posedge
def _activate(self, row_addr):
self.addr.next = row_addr
self.cs.next = False
self.ras.next = False
self.cas.next = True
self.we.next = True
yield self.clk.posedge
def _write(self, addr, val):
self.addr.next = addr
self.wdq.next = val # transaction bus only
self.dqo.next = val # host side driver (controller)
self.cs.next = False
self.ras.next = True
self.cas.next = False
self.we.next = False
yield self.clk.posedge
self.dqo.next = None
def _read(self, addr):
self.addr.next = addr
self.cs.next = False
self.ras.next = True
self.cas.next = False
self.we.next = True
yield self.clk.posedge
if self.dq is not None and self.dqo is None:
self.rdq.next = self.dq
def write(self, val, row_addr, col_addr, bankid=0, burst=1):
""" Controller side write
This is a transaction generator, this generator is used to
emulate a host write to an SDRAM device.
@todo: complete burst transaction
Not convertible.
"""
# start on the posedge of the interface clock
yield self.clk.posedge
self.bs.next = bankid
self.cke.next = True
yield self._nop()
yield self._activate(row_addr)
yield self._nop()
yield self._write(col_addr, val)
yield self._nop()
self.cke.next = False
def read(self, row_addr, col_addr, bankid=0, burst=1):
""" Controller side read
This is a transaction generator, this genertor is used to
emulate a host read to an SDRAM device.
@todo: complete burst transaction
Not convertible.
"""
# start of the posedge of the interface clock
yield self.clk.posedge
self.bs.next = bankid
self.cke.next = True
yield self._nop()
yield self._activate(row_addr)
yield self._nop()
yield self._read(col_addr)
yield self._nop()
self.cke.next = False
self.read_data = int(self.rdq)
def get_read_data(self):
return self.read_data
class SDRAMInterface(object):
clock_frequency = 100e6
timing = { # all timing parameters in ns
'init': 200000.0, # min init interval
'ras': 45.0, # min interval between active precharge commands
'rcd': 20.0, # min interval between active R/W commands
'ref': 64000000.0, # max refresh interval
'rfc': 65.0, # refresh operaiton duration
'rp': 20.0, # min precharge command duration
'xsr': 75.0, # exit self-refresh time
'wr': 55.0, # @todo ...
}
addr_width = 12 # SDRAM address width
data_width = 16 # SDRAM data width
def __init__(self, num_banks=4, addr_width=12, data_width=16, ver='sdr'):
# signals in the interface
self.frequency = 0. # @todo:
self.clk = Signal(bool(0)) # interface clock
self.cke = Signal(bool(0)) # clock enable
self.cs = Signal(bool(0)) # chip select
self.cas = Signal(bool(0)) # column address strobe
self.ras = Signal(bool(0)) # row address strobe
self.we = Signal(bool(0)) # write strobe
self.bs = Signal(intbv(0)[2:]) # bank select
self.addr = Signal(intbv(0)[addr_width:])
self.dqm = Signal(bool(0))
self.dqml = Signal(bool(0))
self.dqmh = Signal(bool(0))
self.dq = TristateSignal(intbv(0)[data_width:])
# the controller and SDRAM bi-dir bus drivers
self.dqo = self.dq.driver()
self.dqi = self.dq.driver()
# the following separate write and read buses are
# not used in an actual device. They are used by
# the model for debug and testing.
self.wdq = Signal(intbv(0)[data_width:])
self.rdq = Signal(intbv(0)[data_width:])
# configurations for the SDRAM interfacing with
self.num_banks = num_banks
self.addr_width = addr_width
self.data_width = data_width
self.ver = ver
# saved read, transactors save the read data here
self.read_data = None
# generic commands for a DRAM, override these for specific (S)DRAM devices
# @todo: attribute of the interface or global definition?
self.Commands = enum(
"NOP", # no operation, ignore all inputs
"ACT", # activate a row in a particular bank
"RD", # read, initiate a read burst to an active row
"WR", # write, initial a write burst to an active row
"PRE", # precharge, close a row in a particular bank
"REF", # refresh, start a refresh operation
# extended commands (???)
"LMR", # load mode register
)
# extract the default timing parameters, all parameters in ns
# but convert to "ps" like ticks.
cycles = {}
for k, v in self.timing.items():
cycles[k] = (v * (self.clock_frequency / 1e9))
# @todo: if 'ddr' in self.ver: cycles[k] *= 2
# add the cycle numbers to the
for k, v in cycles.items():
# majority of the timing parameters are maximum times,
# floor error on the side of margin ...
self.__dict__['cyc_' + k] = int(floor(v))
# convert the time parameters to simulation ticks
# @todo: where to get the global simulation step?
for k, v in self.timing.items():
self.__dict__['tick_' + k] = int(ceil(v * 1000))
def get_data_driver(self, dir='o'):
if dir == 'o':
drv = self.dqo
else:
drv = self.dqi
return drv
def get_command(self):
""" extract the current command from based in the interface signals
Command table
cs ras cas we dqm
H X X X X : NOP (command inhibit)
L H H H X : NOP
L H H L X : (burst term)
L H L H X : RD
L H L L X : WR
L L H H X : ACT
L L H L X : PRE
L L L H X : REF (auto refresh)
L L L L X : LRM (load mode register)
:return:
"""
cs, ras, cas, we, dqm = (self.cs, self.ras, self.cas, self.we,
self.dqm)
cmd = self.Commands.NOP
if not cs:
if ras and not cas and we:
cmd = self.Commands.RD
elif ras and not cas and not we:
cmd = self.Commands.WR
elif not ras and cas and we:
cmd = self.Commands.ACT
elif not ras and cas and not we:
cmd = self.Commands.PRE
elif not ras and not cas and we:
cmd = self.Commands.REF
elif not ras and not cas and not we:
cmd = self.Commands.LRM
return cmd
def _set_cmd(self, cmd):
pass
def _nop(self):
self.cs.next = False
self.ras.next = True
self.cas.next = True
self.we.next = True
yield self.clk.posedge
def _activate(self, row_addr):
self.addr.next = row_addr
self.cs.next = False
self.ras.next = False
self.cas.next = True
self.we.next = True
yield self.clk.posedge
def _write(self, addr, val):
self.addr.next = addr
self.wdq.next = val # transaction bus only
self.dqo.next = val # host side driver (controller)
self.cs.next = False
self.ras.next = True
self.cas.next = False
self.we.next = False
yield self.clk.posedge
self.dqo.next = None
def _read(self, addr):
self.addr.next = addr
self.cs.next = False
self.ras.next = True
self.cas.next = False
self.we.next = True
yield self.clk.posedge
if self.dq is not None and self.dqo is None:
self.rdq.next = self.dq
def write(self, val, row_addr, col_addr, bankid=0, burst=1):
""" Controller side write
This is a transaction generator, this generator is used to
emulate a host write to an SDRAM device.
@todo: complete burst transaction
Not convertible.
"""
# start on the posedge of the interface clock
yield self.clk.posedge
self.bs.next = bankid
self.cke.next = True
yield self._nop()
yield self._activate(row_addr)
yield self._nop()
yield self._write(col_addr, val)
yield self._nop()
self.cke.next = False
def read(self, row_addr, col_addr, bankid=0, burst=1):
""" Controller side read
This is a transaction generator, this generator is used to
emulate a host read to an SDRAM device.
@todo: complete burst transaction
Not convertible.
"""
# start of the posedge of the interface clock
yield self.clk.posedge
self.bs.next = bankid
self.cke.next = True
yield self._nop()
yield self._activate(row_addr)
yield self._nop()
yield self._read(col_addr)
yield self._nop()
self.cke.next = False
self.read_data = int(self.rdq)
def get_read_data(self):
return self.read_data
def __init__(self, num_banks=4, addr_width=12, data_width=16, ver='sdr'):
# signals in the interface
self.frequency = 0. # @todo:
self.clk = Signal(bool(0)) # interface clock
self.cke = Signal(bool(0)) # clock enable
self.cs = Signal(bool(0)) # chip select
self.cas = Signal(bool(0)) # column address strobe
self.ras = Signal(bool(0)) # row address strobe
self.we = Signal(bool(0)) # write strobe
self.bs = Signal(intbv(0)[2:]) # bank select
self.addr = Signal(intbv(0)[addr_width:])
self.dqm = Signal(bool(0))
self.dqml = Signal(bool(0))
self.dqmh = Signal(bool(0))
self.dq = TristateSignal(intbv(0)[data_width:])
# the controller and SDRAM bi-dir bus drivers
self.dqo = self.dq.driver()
self.dqi = self.dq.driver()
# the following separate write and read buses are
# not used in an actual device. They are used by
# the model for debug and testing.
self.wdq = Signal(intbv(0)[data_width:])
self.rdq = Signal(intbv(0)[data_width:])
# configurations for the SDRAM interfacing with
self.num_banks = num_banks
self.addr_width = addr_width
self.data_width = data_width
self.ver = ver
# saved read, transactors save the read data here
self.read_data = None
# generic commands for a DRAM, override these for specific (S)DRAM devices
# @todo: attribute of the interface or global definition?
self.Commands = enum(
"NOP", # no operation, ignore all inputs
"ACT", # activate a row in a particular bank
"RD", # read, initiate a read burst to an active row
"WR", # write, initial a write burst to an active row
"PRE", # precharge, close a row in a particular bank
"REF", # refresh, start a refresh operation
# extended commands (???)
"LMR", # load mode register
)
# extract the default timing parameters, all parameters in ns
# but convert to "ps" like ticks.
cycles = {}
for k, v in self.timing.items():
cycles[k] = (v * (self.clock_frequency / 1e9))
# @todo: if 'ddr' in self.ver: cycles[k] *= 2
# add the cycle numbers to the
for k, v in cycles.items():
# majority of the timing parameters are maximum times,
# floor error on the side of margin ...
self.__dict__['cyc_' + k] = int(floor(v))
# convert the time parameters to simulation ticks
# @todo: where to get the global simulation step?
for k, v in self.timing.items():
self.__dict__['tick_' + k] = int(ceil(v * 1000))
def __init__(self):
self.Y = TristateSignal(True)
self.A = Signal(False)
self.OE = Signal(False)
def get_portmap(self, top=None, **kwargs):
pp = FPGA.get_portmap(self, top, **kwargs)
pp['init_b'] = TristateSignal(False)
print 'hacked pp', pp
return pp
class Mojo(FPGA):
vendor = 'xilinx'
family = 'spartan6'
device = 'XC6SLX9'
package = 'TQG144'
speed = '-2'
version = 3
_name = 'mojov'
no_startup_jtag_clock = True
default_clocks = {
# clk in documentation (?)
'clock': dict(frequency=50e6, pins=(56, ), iostandard='LVTTL')
}
default_resets = {
# rst_n in documentation
'reset': dict(active=0, isasync=True, pins=(38, ), iostandard='LVTTL')
}
default_ports = {
# on-board led
'led':
dict(pins=(
134,
133,
132,
131,
127,
126,
124,
123,
),
iostandard='LVTTL'),
'cclk':
dict(pins=(70, ), iostandard='LVTTL'),
'spi_mosi':
dict(pins=(44, ), iostandard='LVTTL'),
'spi_miso':
dict(pins=(45, ), iostandard='LVTTL'),
'spi_ss':
dict(pins=(48, ), iostandard='LVTTL'),
'spi_sck':
dict(pins=(43, ), iostandard='LVTTL'),
'spi_channel':
dict(pins=(
46,
61,
62,
65,
),
sigtype=TristateSignal(intbv(0)[4:]),
iostandard='LVTTL'),
'avr_tx':
dict(pins=(55, ), iostandard='LVTTL'),
'avr_rx':
dict(pins=(59, ), iostandard='LVTTL'),
'avr_tx_busy':
dict(pins=(39, ), iostandard='LVTTL'),
}
def get_flow(self, top=None):
return ISE(brd=self, top=top)
