def bind_arc(self, net, uphill_wire, arc, config): dest_wire, configurable, tile = arc assert (dest_wire not in self.wire_to_net) or (self.wire_to_net[dest_wire] == net) self.wire_to_net[dest_wire] = net exists = False if net in self.net_to_wire: exists = dest_wire in self.net_to_wire[net] self.net_to_wire[net].add(dest_wire) else: self.net_to_wire[net] = {dest_wire} if configurable and not exists: src_wirename = nets.normalise_name(self.chip_size, tile, uphill_wire, 0) sink_wirename = nets.normalise_name(self.chip_size, tile, dest_wire, 0) config[tile].add_arc(sink_wirename, src_wirename)
def get_fanout(net): drivers = [] npos = tiles.pos_from_name(net) for tile in c.get_all_tiles(): tinf = tile.info tname = tinf.name pos = tiles.pos_from_name(tname) if abs(pos[0] - npos[0]) >= 12 or abs(pos[1] - npos[1]) >= 12: continue if net.startswith("G_"): tnet = net else: tnet = nets.normalise_name(chip_size, tname, net) tdb = pytrellis.get_tile_bitdata( pytrellis.TileLocator(c.info.family, c.info.name, tinf.type)) for sink in tdb.get_sinks(): mux = tdb.get_mux_data_for_sink(sink) if tnet in mux.arcs: drivers.append( (nets.canonicalise_name(chip_size, tname, sink), True, tname)) for fc in tdb.get_fixed_conns(): if fc.source == tnet: drivers.append( (nets.canonicalise_name(chip_size, tname, fc.sink), False, tname)) return drivers
def get_fanin(net): drivers = [] npos = tiles.pos_from_name(net, chip_size, bias) for tile in c.get_all_tiles(): tinf = tile.info tname = tinf.name pos = tiles.pos_from_name(tname, chip_size, bias) if abs(pos[0] - npos[0]) >= 10 or abs(pos[1] - npos[1]) >= 10: continue if net.startswith("G_"): tnet = net else: tnet = nets.normalise_name(chip_size, tname, net, bias) tdb = pytrellis.get_tile_bitdata( pytrellis.TileLocator(c.info.family, c.info.name, tinf.type)) try: mux = tdb.get_mux_data_for_sink(tnet) for src in mux.get_sources(): drivers.append( (nets.canonicalise_name(chip_size, tname, src, bias), True, tname)) except IndexError: pass for fc in tdb.get_fixed_conns(): if fc.sink == tnet: drivers.append( (nets.canonicalise_name(chip_size, tname, fc.source, bias), False, tname)) return drivers
def get_arcs_downhill(self, wire): if wire in self.dh_arc_cache: return self.dh_arc_cache[wire] else: drivers = [] chip_size = (self.chip.get_max_row(), self.chip.get_max_col()) try: npos = tiles.pos_from_name(wire, chip_size, self.bias) except AssertionError: return [] wname = wire.split("_", 1)[1] hspan = 0 vspan = 0 if wname.startswith("H") and wname[1:3].isdigit(): hspan = int(wname[1:3]) if wname.startswith("V") and wname[1:3].isdigit(): vspan = int(wname[1:3]) positions = {(npos[0], npos[1]), (npos[0] + vspan, npos[1]), (npos[0] - vspan, npos[1]), (npos[0], npos[1] + hspan), (npos[0], npos[1] - hspan)} for pos in positions: for tile in self.chip.get_tiles_by_position(pos[0], pos[1]): tinf = tile.info tname = tinf.name if tname.startswith("TAP"): continue pos = tiles.pos_from_name(tname, chip_size, self.bias) if abs(pos[0] - npos[0]) not in ( vspan, 0) or abs(pos[1] - npos[1]) not in (hspan, 0): continue if wire.startswith("G_"): twire = wire else: twire = nets.normalise_name(self.chip_size, tname, wire, self.bias) tdb = pytrellis.get_tile_bitdata( pytrellis.TileLocator(self.chip.info.family, self.chip.info.name, tinf.type)) downhill = tdb.get_downhill_wires(twire) for sink in downhill: nn = nets.canonicalise_name(self.chip_size, tname, sink.first, self.bias) if nn is not None: drivers.append((nn, sink.second, tname)) self.dh_arc_cache[wire] = drivers return drivers
def normalise_arc_in_tile(tile, arc): return tuple(nets.normalise_name((max_row, max_col), tile, x) for x in arc)