Example #1
0
    def test_redundant_paths_spinn7_via_router_require_turn():
        the_machine = machine.Machine('spinn-7', type="spinn4")
        src_vertex_constraints = lib_map.VertexConstraints(x=0, y=0)
        src_vrt = graph.Vertex(1,models.IF_curr_exp,
                               constraints=src_vertex_constraints)
        src_sub_vert = graph.Subvertex(src_vrt, 0,1)

        dest_vertex_constraints = lib_map.VertexConstraints(x=2, y=3)
        dest_vrt = graph.Vertex(1,models.IF_curr_exp,
                                constraints=dest_vertex_constraints)
        dest_sub_vert = graph.Subvertex(dest_vrt, 0,1)
        dest_sub_vert2 = graph.Subvertex(dest_vrt, 0,1)

        edge = graph.Edge(None, src_vrt, dest_vrt)
        sbedge = graph.Subedge(edge, src_sub_vert, dest_sub_vert)
        sbedge2 = graph.Subedge(edge, src_sub_vert, dest_sub_vert2)

        dao_object = dao
        #place vertexes in correct cores
        placements = Placer.place_raw(the_machine,
                                             [src_sub_vert, dest_sub_vert,
                                              dest_sub_vert2])
        dao.placements = placements
        routings = dijkstra_routing.DijkstraRouting.\
            route_raw(the_machine, [src_sub_vert, dest_sub_vert, dest_sub_vert2])
        inconsistant_routings, redundant_paths = \
            Router.check_for_inconsistant_routings(the_machine)
        assert(len(redundant_paths) > 0)
        assert(len(inconsistant_routings) == 0)
        Router.redundant_path_removal(redundant_paths, the_machine)
        inconsistant_routings, redundant_paths = \
            Router.check_for_inconsistant_routings(the_machine)
        assert(len(redundant_paths) == 0)
        assert(len(inconsistant_routings) == 0)
Example #2
0
    def test_redundant_paths_spinn7_via_router_same_chip():
        the_machine = machine.Machine('spinn-7', type="spinn4")
        src_vertex_constraints = lib_map.VertexConstraints(x=0, y=0, p=2)
        src_vrt = graph.Vertex(1, models.IF_curr_exp,
                               constraints=src_vertex_constraints)
        src_sub_vert = graph.Subvertex(src_vrt, 0,1)

        dest_vertex_constraints = lib_map.VertexConstraints(x=0, y=0, p=5)
        dest_vrt = graph.Vertex(1, models.IF_curr_exp,
                                constraints=dest_vertex_constraints)
        dest_sub_vert = graph.Subvertex(dest_vrt, 0,1)
        dest_sub_vert2 = graph.Subvertex(dest_vrt, 0,1)

        dest_vertex_constraints2 = lib_map.VertexConstraints(x=0, y=0, p=6)
        dest_vrt2 = graph.Vertex(1, models.IF_curr_exp,
                                 constraints=dest_vertex_constraints2)
        dest_sub_vert2 = graph.Subvertex(dest_vrt2, 0, 1)

        edge = graph.Edge(None, src_vrt, dest_vrt)
        sbedge = graph.Subedge(edge, src_sub_vert, dest_sub_vert)
        sbedge2 = graph.Subedge(edge, src_sub_vert, dest_sub_vert2)

        dao_object = dao
        #place vertexes in correct cores
        placements = Placer.place_raw(the_machine,
                                             [src_sub_vert, dest_sub_vert,
                                              dest_sub_vert2])
        dao.placements = placements
        routings = dijkstra_routing.\
            DijkstraRouting.route_raw(the_machine,
                                      [src_sub_vert, dest_sub_vert,
                                       dest_sub_vert2])
        inconsistant_routings, redundant_paths = \
            Router.check_for_inconsistant_routings(the_machine)
        assert(len(redundant_paths) > 0)
        assert(len(inconsistant_routings) == 0)
        #print "entry {} and entry {}".format(redundant_paths[0][2].route, redundant_paths[0][3].route)
        Router.redundant_path_removal(redundant_paths, the_machine)
        inconsistant_routings, redundant_paths = \
            Router.check_for_inconsistant_routings(the_machine)
        assert(len(redundant_paths) == 0)
        assert(len(inconsistant_routings) == 0)
        for key in the_machine.chips[0][0].router.cam.keys():
            entry_list = the_machine.chips[0][0].router.cam.get(key)
            assert(len(entry_list) == 1)
            #print "entry is {}".format(entry_list[0].route)
            assert(entry_list[0].route == 6144)