def __init__(self): self.run = Port(bool, 'in', protocol='ready_valid') self.result = Port(int, 'out', protocol='ready_valid') self.din = Queue(int32, 'in') self.dout = Queue(int32, 'out') self.append_worker(self.mips_main)
def __init__(self, data_size): self.i_q = Queue(uint16, 'in', maxsize=data_size) self.o_q = Queue(uint16, 'out', maxsize=data_size) tmp_q0 = Queue(uint16, 'any', maxsize=data_size) tmp_q1 = Queue(uint16, 'any', maxsize=data_size) self.append_worker(mul, 2, data_size, self.i_q, tmp_q0) self.append_worker(mul, 3, data_size, tmp_q0, tmp_q1) self.append_worker(mul, 4, data_size, tmp_q1, self.o_q)
class Port03: def __init__(self): self.in_q = Queue(int8, 'in', maxsize=2) self.out_q = Queue(int8, 'out', maxsize=2) self.append_worker(self.main) def main(self): while is_worker_running(): d = self.in_q.rd() self.out_q.wr(d)
class parameter01: def __init__(self, PARAM0, PARAM1:uint8=2): self.p0 = PARAM0 self.p1 = PARAM0 + PARAM1 self.o0 = Queue(int, 'out') self.o1 = Queue(int, 'out') self.append_worker(self.w) def w(self): self.o0.wr(self.p0) self.o1.wr(self.p1)
class queue05: def __init__(self): self.in_q = Queue(int8, 'in', maxsize=2) self.out_q = Queue(int8, 'out', maxsize=2) self.append_worker(self.main) def main(self): while is_worker_running(): if not self.in_q.empty(): d = self.in_q.rd() if not self.out_q.full(): self.out_q.wr(d)
def __init__(self, start_addr, end_addr): # define i/o self.dout = Port(int8, 'out', protocol='ready_valid') # define internals instq = Queue(uint16, 'any', maxsize=2) opeq = Queue(uint8, 'any', maxsize=2) valueq = Queue(uint8, 'any', maxsize=2) self.append_worker(fetch, start_addr, end_addr, instq) self.append_worker(decode, instq, opeq, valueq) self.append_worker(execute, opeq, valueq, self.dout)
class worker_with_tuple: def __init__(self): self.i = Queue(bit8, 'in') self.o = Queue(bit8, 'out') self.append_worker(self.worker) def func(self, a, b): return (a, b) def worker(self): while is_worker_running(): d0 = self.i.rd() d1 = self.i.rd() a, b = self.func(d0, d1) self.o.wr(a + b)
class busy_loop: def __init__(self): self.i = Queue(int, 'in') self.append_worker(self.w) def w(self): while is_worker_running(): while True: d = self.i.rd() assert d == 0 d = self.i.rd() assert d == 1 d = self.i.rd() assert d == 2 while True: d = self.i.rd()
class sha256: def __init__(self): self.data_in = Queue(bit512, 'in') self.data_out = Queue(bit512, 'out') self.do_digest = Port(bit, 'in', protocol='none') self.do_digest_ack = Port(bit, 'out', protocol='none') self.append_worker(self.process_sha256) def process_sha256(self): work = [0] * 64 # type: List[bit32] _h = [0] * 8 # type: List[bit32] __h = [0] * 8 # type: List[bit32] while is_worker_running(): v512 = bit32x8_bit512(_h) self.data_out.wr(v512)
class io_conflict02: def __init__(self): self.p = Queue(int, 'in') self.append_worker(self.w) def w(self): data = self.p.rd() print(data)
class Filter: def __init__(self): #self.uart = uart.Transmitter() #self.spi_in = AD7091R_SPIC() self.q = Queue(uint16, 'out', maxsize=10) self.din = Queue(uint16, 'in', maxsize=10) self.append_worker(self.proc) @rule(scheduling='pipeline') def proc(self): a0: uint18 = 0 a1: uint18 = 0 a2: uint18 = 0 a3: uint18 = 0 while is_worker_running(): self.q.wr(a0 >> 2) data: uint16 = self.din.rd() a0 = a1 + data a1 = a2 + data a2 = a3 + data a3 = data
class M: ONE = 1 TWO = 2 THREE = 3 def __init__(self): self.out = Queue(int, 'out') self.append_worker(self.worker) def worker(self): while is_worker_running(): self.out.wr(self.func(1)) self.out.wr(self.func(2)) self.out.wr(self.func(3)) def func(self, v): if v == 1: return self.ONE elif v == 2: return self.TWO else: return self.THREE
class queue06: def __init__(self): self.in_cmd = Queue(int8, 'in', maxsize=2) self.din0 = Port(int, 'in') self.din1 = Port(int, 'in') self.out_q = Queue(int8, 'out', maxsize=2) self.append_worker(self.main) def calc(self, cmd): if cmd == 0: return self.din0.rd() + self.din1.rd() elif cmd == 1: return self.din0.rd() - self.din1.rd() elif cmd == 2: return self.din0.rd() * self.din1.rd() return 0 def main(self): while is_worker_running(): if not self.in_cmd.empty(): cmd = self.in_cmd.rd() ret = self.calc(cmd) if not self.out_q.full(): self.out_q.wr(ret)
class queue04: def __init__(self): self.in_q = Queue(int8, 'in', maxsize=2) self.out_q = Queue(int8, 'out', maxsize=2) self.tmp_q = Queue(int8, 'any', maxsize=2) self.append_worker(self.worker1) self.append_worker(self.worker2) def worker1(self): while is_worker_running(): d = self.in_q.rd() self.tmp_q.wr(d) def worker2(self): while is_worker_running(): d = self.tmp_q.rd() self.out_q.wr(d)
class sha256: def __init__(self): self.data_in = Queue(bit512, 'in') self.data_out = Queue(bit256, 'out') self.append_worker(self.process_sha256) def process_sha256(self): work = [0] * 64 # type: List[bit32] _h = [0] * 8 # type: List[bit32] __h = [0] * 8 # type: List[bit32] while is_worker_running(): update = True for i in range(8): _h[i] = h[i] block_len512: bit512 = self.data_in.rd() block_len32 = block_len512 count = 0 #print(block_len512) #print(block_len32) while count < block_len32: #print(count, block_len32) count += 1 #print("--=========") d512 = self.data_in.rd() #print("start d512 %5t", d512, "$time") shift_n = 480 for i in unroll(range(16)): work[i] = (d512 >> shift_n) & 0xFFFFFFFF shift_n -= 32 for i in range(16, 64): wi_15 = work[i - 15] s0 = rotr(wi_15, 7) ^ rotr(wi_15, 18) ^ (wi_15 >> 3) wi_2 = work[i - 2] s1 = rotr(wi_2, 17) ^ rotr(wi_2, 19) ^ (wi_2 >> 10) wi_16 = work[i - 16] wi_7 = work[i - 7] work[i] = (wi_16 + s0 + wi_7 + s1) & 0xFFFFFFFF with rule(unroll='full'): for i in range(8): __h[i] = _h[i] for i in range(64): s0 = rotr(__h[0], 2) ^ rotr(__h[0], 13) ^ rotr(__h[0], 22) maj = (__h[0] & __h[1]) ^ (__h[0] & __h[2]) ^ (__h[1] & __h[2]) t2 = s0 + maj s1 = rotr(__h[4], 6) ^ rotr(__h[4], 11) ^ rotr(__h[4], 25) ch = (__h[4] & __h[5]) ^ ((~__h[4]) & __h[6]) t1 = __h[7] + s1 + ch + k[i] + work[i] __h[7] = __h[6] __h[6] = __h[5] __h[5] = __h[4] __h[4] = (__h[3] + t1) & 0xFFFFFFFF __h[3] = __h[2] __h[2] = __h[1] __h[1] = __h[0] __h[0] = (t1 + t2) & 0xFFFFFFFF with rule(unroll='full'): for i in range(8): _h[i] = (_h[i] + __h[i]) & 0xFFFFFFFF # print("turn %5t", count, "$time") rv256: bit256 = 0 with rule(unroll='full'): for i in range(8): rv256 <<= 32 rv256 |= _h[i] #print("rv256 %5t", rv256, "$time") self.data_out.wr(rv256)
def __init__(self): self.in_cmd = Queue(int8, 'in', maxsize=2) self.din0 = Port(int, 'in') self.din1 = Port(int, 'in') self.out_q = Queue(int8, 'out', maxsize=2) self.append_worker(self.main)
def __init__(self): self.data_in = Queue(bit512, 'in') self.data_out = Queue(bit256, 'out') self.append_worker(self.process_sha256)
def __init__(self): self.in_q = Queue(int8, 'in', maxsize=2) self.out_q = Queue(int8, 'out', maxsize=2) tmp_q = Queue(int8, 'any', maxsize=2) self.append_worker(self.main, self.in_q, tmp_q) self.append_worker(self.main, tmp_q, self.out_q)
def __init__(self): self.in_q = Queue(int8, 'in', maxsize=2) self.out_q = Queue(int8, 'out', maxsize=2) self.tmp_q = Queue(int8, 'any', maxsize=2) self.append_worker(self.worker1) self.append_worker(self.worker2)
def __init__(self, width, height, blank_size): self.inq = Queue(int12, 'in', maxsize=4) #self.outhq = Queue(int12, 'out', maxsize=4) #self.outvq = Queue(int12, 'out', maxsize=4) self.outq = Queue(int12, 'out', maxsize=4) self.append_worker(self.worker, width, height, blank_size)
def __init__(self): self.p = Queue(int, 'in') self.append_worker(self.w) self.append_worker(self.w)
def __init__(self): self.out = Queue(int, 'out') self.append_worker(self.worker)
def __init__(self): self.i_q = Queue(int, 'in') self.o_q = Queue(int, 'out') self.append_worker(self.w, self.i_q, self.o_q)
def __init__(self, PARAM0, PARAM1:uint8=2): self.p0 = PARAM0 self.p1 = PARAM0 + PARAM1 self.o0 = Queue(int, 'out') self.o1 = Queue(int, 'out') self.append_worker(self.w)
def __init__(self): self.i = Queue(bit8, 'in') self.o = Queue(bit8, 'out') self.append_worker(self.worker)
class PipelinedStreamFilter: def __init__(self, width, height, blank_size): self.inq = Queue(int12, 'in', maxsize=4) #self.outhq = Queue(int12, 'out', maxsize=4) #self.outvq = Queue(int12, 'out', maxsize=4) self.outq = Queue(int12, 'out', maxsize=4) self.append_worker(self.worker, width, height, blank_size) def worker(self, width, height, blank_size): buf0: List[int12] = [255] * (width + blank_size) buf1: List[int12] = [255] * (width + blank_size) buf2: List[int12] = [255] * (width + blank_size) line0 = buf0 line1 = buf1 line2 = buf2 phase = 0 y = blank_size r0: int12 = 255 r1: int12 = 255 r2: int12 = 255 r3: int12 = 255 r4: int12 = 255 r5: int12 = 255 r6: int12 = 255 r7: int12 = 255 r8: int12 = 255 while is_worker_running(): for x in pipelined(range(blank_size, width + blank_size)): #for x in range(blank_size, width + blank_size): d2 = self.inq.rd() line2[x] = d2 d1 = line1[x] d0 = line0[x] r0, r1, r2 = r1, r2, d0 r3, r4, r5 = r4, r5, d1 r6, r7, r8 = r7, r8, d2 out_h = filter3x3(r0, r1, r2, r3, r4, r5, r6, r7, r8, K_H) out_v = filter3x3(r0, r1, r2, r3, r4, r5, r6, r7, r8, K_V) #out_h_c = clip(128 + out_h) #out_v_c = clip(128 + out_v) out_c = clip(abs(out_h) + abs(out_v) >> 1) #self.outhq.wr(out_h_c) #self.outvq.wr(out_v_c) self.outq.wr(out_c) phase = (phase + 1) % 3 if phase == 0: line0 = buf0 line1 = buf1 line2 = buf2 elif phase == 1: line0 = buf1 line1 = buf2 line2 = buf0 else: line0 = buf2 line1 = buf0 line2 = buf1 r0 = r1 = r2 = 255 r3 = r4 = r5 = 255 r6 = r7 = r8 = 255 y += 1 if y == height + blank_size: # TODO: break
def __init__(self): self.in_q = Queue(int8, 'in', maxsize=2) self.out_q = Queue(int8, 'out', maxsize=2) self.append_worker(self.main)
def __init__(self): p = Queue(int) self.append_worker(self.w, p) self.append_worker(self.w, p)
def __init__(self): self.o1_q = Queue(uint16, 'out', maxsize=1) self.o2_q = Queue(uint16, 'out', maxsize=1) self.append_worker(self.w, self.o1_q, self.o2_q)
def __init__(self): #self.uart = uart.Transmitter() #self.spi_in = AD7091R_SPIC() self.q = Queue(uint16, 'out', maxsize=10) self.din = Queue(uint16, 'in', maxsize=10) self.append_worker(self.proc)