Example #1
0
    def test_fir_design(self):
        in_sign = Signature("in", True, bits=9)
        out_sign = Signature("out", True, bits=9)

        s = FirSim(in_sign=in_sign, out_sign=out_sign)
        taps = [int(t) for t in s.design(48e3, 12e3, 1e3, 40.0)]

        in_c = s.input_signal()
        in_t = arange(len(in_c))
        in_i = [int(i.real * (2**8-1)) for i in in_c]
        in_q = [int(i.imag * (2**8-1)) for i in in_c]

        s.verify_design()

        coeff_ram = Ram2(s.clearn, s.clock, s.clock, data=taps)
        delay_line_i_ram = Ram(s.clearn, s.clock, s.clock)
        delay_line_q_ram = Ram(s.clearn, s.clock, s.clock)
        bypass = Signal(bool(0))
        bank1 = Signal(bool(0))
        bank0 = Signal(bool(0))
        N = Signal(intbv(len(taps), min=0, max=2**7-1))

        def test_fir_design():
            load_coeff_ram_addr = coeff_ram.port['b'].addr
            load_coeff_ram_blk = coeff_ram.port['b'].blk
            load_coeff_ram_wen = coeff_ram.port['b'].wen
            fir_0 = fir(s.clearn, s.clock, s.input, s.output,
                    coeff_ram.port['a'].addr,
                    coeff_ram.port['a'].din[0],
                    coeff_ram.port['a'].din[1],
                    coeff_ram.port['a'].blk,
                    coeff_ram.port['a'].wen,
                    coeff_ram.port['a'].dout[0],
                    coeff_ram.port['a'].dout[1],
                    delay_line_i_ram.port['a'].addr,
                    delay_line_i_ram.port['a'].din,
                    delay_line_i_ram.port['a'].blk,
                    delay_line_i_ram.port['a'].wen,
                    delay_line_i_ram.port['a'].dout,
                    delay_line_q_ram.port['a'].addr,
                    delay_line_q_ram.port['a'].din,
                    delay_line_q_ram.port['a'].blk,
                    delay_line_q_ram.port['a'].wen,
                    delay_line_q_ram.port['a'].dout,
                    bypass, bank1, bank0, N,
                    sim=s)

            return fir_0, coeff_ram.rama, coeff_ram.ramb, delay_line_i_ram.ram, delay_line_q_ram.ram

        out_i, out_q = s.simulate_quadrature(in_i, in_q, test_fir_design, interp=128)
        out_t = arange(0, out_i.shape[0])

        new_shape = tuple([in_t.shape[i] for i in range(len(in_t.shape))])
        assert out_t.shape == new_shape
        f = figure("fir_output")
        title("fir filter output")
        f_out = figure_discrete_quadrature('FIR Filter Output', (1, 1, 1), f, s.input, out_t, out_i / (2.**8-1), out_q / (2.**8-1))
        savefig('output.png')
Example #2
0
    def test_fir_bypass(self):
        in_sign = Signature("in", True, bits=9)
        out_sign = Signature("out", True, bits=9)

        s = FirSim(in_sign=in_sign, out_sign=out_sign)
        s.design(48e3, 6e3, 1e3, 40.0)
        s.input_signal()

        taps = (4 << COEFF_SHIFT, 3 << COEFF_SHIFT, 2 << COEFF_SHIFT, 1 << COEFF_SHIFT)
        coeff_ram = Ram2(s.clearn, s.clock, s.clock, data=taps)
        delay_line_i_ram = Ram(s.clearn, s.clock, s.clock)
        delay_line_q_ram = Ram(s.clearn, s.clock, s.clock)
        bypass = Signal(bool(1))
        bank1 = Signal(bool(0))
        bank0 = Signal(bool(0))
        N = Signal(intbv(4, min=0, max=2**7-1))

        def test_fir_bypass():
            load_coeff_ram_addr = coeff_ram.port['b'].addr
            load_coeff_ram_blk = coeff_ram.port['b'].blk
            load_coeff_ram_wen = coeff_ram.port['b'].wen
            fir_0 = fir(s.clearn, s.clock, s.input, s.output,
                    coeff_ram.port['a'].addr,
                    coeff_ram.port['a'].din[0],
                    coeff_ram.port['a'].din[1],
                    coeff_ram.port['a'].blk,
                    coeff_ram.port['a'].wen,
                    coeff_ram.port['a'].dout[0],
                    coeff_ram.port['a'].dout[1],
                    delay_line_i_ram.port['a'].addr,
                    delay_line_i_ram.port['a'].din,
                    delay_line_i_ram.port['a'].blk,
                    delay_line_i_ram.port['a'].wen,
                    delay_line_i_ram.port['a'].dout,
                    delay_line_q_ram.port['a'].addr,
                    delay_line_q_ram.port['a'].din,
                    delay_line_q_ram.port['a'].blk,
                    delay_line_q_ram.port['a'].wen,
                    delay_line_q_ram.port['a'].dout,
                    bypass, bank1, bank0, N,
                    sim=s)

            return fir_0, coeff_ram.ram, delay_line_i_ram.ram, delay_line_q_ram.ram

        in_t = arange(0, 8)

        in_c = 0*in_t + 1j * 0*in_t
        in_i = 0*in_t
        in_q = 0*in_t
        in_i[0] = 1 << COEFF_SHIFT
        in_i[4] = 1 << COEFF_SHIFT

        out_i, out_q = s.simulate_quadrature(in_i, in_q, test_fir_bypass, interp=128)
        out_t = arange(0, out_i.shape[0])

        new_shape = tuple([in_t.shape[i] for i in range(len(in_t.shape))])
        assert out_t.shape == new_shape
        assert array_equal(out_i >> 5, array([1, 0, 0, 0, 1, 0, 0, 0]))
Example #3
0
def top(clk, rst, spi_bus):
    from myhdl import instance, delay

    ram = Ram(addr_depth = 5, data_width = 8)

    wb_bus = ram.create_bus()
    wb_bus.CLK_I = clk

    if rst:
        wb_bus.RST_I = rst
    else:
        wb_bus.RST_I = None

    ram_inst = ram.gen(wb_bus)

    spi = SpiSlave()
    spi_inst = spi.gen(spi_bus, wb_bus)

    test_inst = spi_test(spi_bus)

    return ram_inst, spi_inst, test_inst
Example #4
0
def top(clk, rst, spi_bus):
    from myhdl import instance, delay

    ram = Ram(addr_depth=5, data_width=8)

    wb_bus = ram.create_bus()
    wb_bus.CLK_I = clk

    if rst:
        wb_bus.RST_I = rst
    else:
        wb_bus.RST_I = None

    ram_inst = ram.gen(wb_bus)

    spi = SpiSlave()
    spi_inst = spi.gen(spi_bus, wb_bus)

    test_inst = spi_test(spi_bus)

    return ram_inst, spi_inst, test_inst
Example #5
0
 def __init__(self, bus):
     self.bus = bus
     self.clear_enable = Signal(bool(0))
     self.dac2x_clock = Signal(bool(0))
     self.dac_clock = Signal(bool(0))
     self.dac_data = Signal(intbv(0)[10:])
     self.dac_en = Signal(bool(0))
     self.adc_idata = Signal(intbv(0, min=-2**9, max=2**9))
     self.adc_qdata = Signal(intbv(0, min=-2**9, max=2**9))
     self.tx_status_led = Signal(bool(0))
     self.tx_dmaready = Signal(bool(1))
     self.rx_status_led = Signal(bool(0))
     self.rx_dmaready = Signal(bool(1))
     self.tx_q = []
     self.tx_i = []
     self.tx_n = []
     pclk = self.bus.pclk
     self.fir_coeff_ram = Ram2(self.bus.presetn, self.dac_clock, pclk)
     self.fir_delay_line_i_ram = Ram(self.bus.presetn, self.dac_clock,
                                     self.dac_clock)
     self.fir_delay_line_q_ram = Ram(self.bus.presetn, self.dac_clock,
                                     self.dac_clock)
Example #6
0
from mustang import Mustang
from ram import Ram
from leaf import Leaf
from crosstrek import Crosstrek

mach1 = Mustang()
mach1.refuel()
mach1.drive()
mach1.drive()

cummins = Ram()
cummins.refuel()
cummins.drive()
cummins.drive()

hippie = Leaf()
hippie.refuel()
hippie.drive()
hippie.drive()

busaru = Crosstrek()
busaru.refuel()
busaru.drive()
busaru.drive()
Example #7
0
    rx_dmaready = Signal(bool(1))

    bus = Apb3Bus()
    bus_presetn = bus.presetn
    bus_pclk = bus.pclk
    bus_paddr = bus.paddr
    bus_psel = bus.psel
    bus_penable = bus.penable
    bus_pwrite = bus.pwrite
    bus_pwdata = bus.pwdata
    bus_pslverr = bus.pslverr
    bus_pready = bus.pready
    bus_prdata = bus.prdata

    fir_coeff_ram = Ram2(clearn, dac_clock, bus.pclk)
    fir_delay_line_i_ram = Ram(clearn, dac_clock, dac_clock)
    fir_delay_line_q_ram = Ram(clearn, dac_clock, dac_clock)

    tx_fifo_re = Signal(bool(False))
    tx_fifo_rclk = Signal(bool(False))
    tx_fifo_rdata = Signal(intbv(0)[32:])
    tx_fifo_we = Signal(bool(False))
    tx_fifo_wclk = Signal(bool(False))
    tx_fifo_wdata = Signal(intbv(0)[32:])
    tx_fifo_full = Signal(bool(False))
    tx_fifo_afull = Signal(bool(False))
    tx_fifo_empty = Signal(bool(True))
    tx_fifo_aempty = Signal(bool(True))
    tx_fifo_afval = Signal(intbv(fifo_depth - 1)[10:])
    tx_fifo_aeval = Signal(intbv(0)[10:])
    tx_fifo_wack = Signal(bool(False))
Example #8
0
    def test_fir_impulse(self):
        in_sign = Signature("in", True, bits=9)
        out_sign = Signature("out", True, bits=9)

        s = FirSim(in_sign=in_sign, out_sign=out_sign)
        #s.design(48e3, 6e3, 1e3, 40.0)
        taps = (4 << COEFF_SHIFT, 3 << COEFF_SHIFT, 2 << COEFF_SHIFT,
                1 << COEFF_SHIFT)
        coeff_ram = Ram(s.clearn,
                        s.clock,
                        s.clock,
                        data=taps,
                        width=18,
                        depth=512)
        delay_line_i_ram = Ram(s.clearn, s.clock, s.clock, width=9, depth=512)
        delay_line_q_ram = Ram(s.clearn, s.clock, s.clock, width=9, depth=512)
        enable = Signal(bool(1))
        bank1 = Signal(bool(0))
        bank0 = Signal(bool(0))
        N = Signal(intbv(4, min=0, max=2**7 - 1))

        coeff_ram_inst = coeff_ram.instance_type()(
            **coeff_ram.instance_signals())
        delay_line_i_ram_inst = delay_line_i_ram.instance_type()(
            **delay_line_i_ram.instance_signals())
        delay_line_q_ram_inst = delay_line_q_ram.instance_type()(
            **delay_line_q_ram.instance_signals())

        def test_fir_impulse():
            load_coeff_ram_addr = coeff_ram.port['b'].addr
            load_coeff_ram_blk = coeff_ram.port['b'].blk
            load_coeff_ram_wen = coeff_ram.port['b'].wen
            fir_0 = fir(s.clearn,
                        s.clock,
                        s.input,
                        s.output,
                        coeff_ram.port['a'].addr,
                        coeff_ram.port['a'].din,
                        coeff_ram.port['a'].blk,
                        coeff_ram.port['a'].wen,
                        coeff_ram.port['a'].dout,
                        delay_line_i_ram.port['a'].addr,
                        delay_line_i_ram.port['a'].din,
                        delay_line_i_ram.port['a'].blk,
                        delay_line_i_ram.port['a'].wen,
                        delay_line_i_ram.port['a'].dout,
                        delay_line_q_ram.port['a'].addr,
                        delay_line_q_ram.port['a'].din,
                        delay_line_q_ram.port['a'].blk,
                        delay_line_q_ram.port['a'].wen,
                        delay_line_q_ram.port['a'].dout,
                        enable,
                        bank1,
                        bank0,
                        N,
                        sim=s)

            return fir_0, coeff_ram_inst, delay_line_i_ram_inst, delay_line_q_ram_inst

        in_t = arange(0, 8)

        in_c = 0 * in_t + 1j * 0 * in_t
        in_i = 0 * in_t
        in_q = 0 * in_t
        in_i[0] = 1 << 5
        in_i[4] = 1 << 5

        out_i, out_q = s.simulate(in_i, in_q, test_fir_impulse, 128, coeff_ram,
                                  taps)
        out_t = arange(0, out_i.shape[0])

        new_shape = tuple([in_t.shape[i] for i in range(len(in_t.shape))])
        assert out_t.shape == new_shape
        print 'out_i', out_i
        assert array_equal(out_i, [4, 3, 2, 1, 4, 3, 2, 1])
Example #9
0
class Hack(object):
    A_INSTRUCTION = 4096
    LOAD_OP = -32768

    DEST_A = 32
    DEST_D = 16
    DEST_M = 8

    JGT = 1
    JEQ = 2
    JGE = 3
    JLT = 4
    JNE = 5
    JLE = 6
    JMP = 7

    D_BITWISE_AND_MEM = 0
    D_BITWISE_OR_MEM = 1344
    CONSTANT_ZERO = 2688
    CONSTANT_ONE = 4032
    CONSTANT_NEG_ONE = 3712
    D_REG = 768
    MEM_REG = 3072
    NOT_D = 832
    NOT_MEM = 3136
    NEG_D = 960
    NEG_MEM = 3264
    INCR_D = 1984
    INCR_MEM = 3520
    DEC_D = 896
    DEC_MEM = 3200
    D_PLUS_MEM = 128
    D_MINUS_MEM = 1216
    MEM_MINUS_D = 448

    INSTR_MASK = 4032
    JUMP_MASK = 7
    DEST_MASK = 56
    A_INSTR_MASK = 0x8000
    LOAD_MASK = 4096

    def __init__(self, data=None, fromq=None, toq=None):
        self.ram = Ram(32768, fromq, toq)
        self.rom = Rom(32768, data=data)
        self.register_a = Register()
        self.register_d = Register()
        self.program_counter = Register()

    def execute(self):
        if self.c_instruction:
            d = self.register_d.value
            if self.from_ram:
                mem = self.ram[self.register_a.value]
            else:
                mem = self.register_a.value
            comp = self.get_comp(d, mem)
            self.store_value(comp)
            self.program_counter.value = self.get_next(comp)
        else:
            self.register_a.value = self.instruction
            self.program_counter.value = self.program_counter.value + 1
        self.ram.update_key_buffer()

    def get_comp(self, d, mem):
        if self.op == self.CONSTANT_ZERO:
            return 0
        elif self.op == self.CONSTANT_ONE:
            return 1
        elif self.op == self.CONSTANT_NEG_ONE:
            return -1
        elif self.op == self.D_REG:
            return d
        elif self.op == self.MEM_REG:
            return mem
        elif self.op == self.NOT_D:
            return ~d
        elif self.op == self.NOT_MEM:
            return ~mem
        elif self.op == self.NEG_D:
            return -1 * d
        elif self.op == self.NEG_MEM:
            return -1 * mem
        elif self.op == self.INCR_D:
            return d + 1
        elif self.op == self.INCR_MEM:
            return mem + 1
        elif self.op == self.DEC_D:
            return d - 1
        elif self.op == self.DEC_MEM:
            return mem - 1
        elif self.op == self.D_PLUS_MEM:
            return mem + d
        elif self.op == self.D_MINUS_MEM:
            return d - mem
        elif self.op == self.MEM_MINUS_D:
            return mem - d
        elif self.op == self.D_BITWISE_OR_MEM:
            return mem | d
        else:
            return d & mem

    def store_value(self, comp):
        if self.store_m:
            self.ram[self.register_a.value] = comp
        if self.store_d:
            self.register_d.value = comp
        if self.store_a:
            self.register_a.value = comp

    def get_next(self, comp):
        jump = False
        if self.jump == 1 and comp > 0:
            jump = True
        elif self.jump == 2 and comp == 0:
            jump = True
        elif self.jump == 3 and comp >= 0:
            jump = True
        elif self.jump == 4 and comp < 0:
            jump = True
        elif self.jump == 5 and comp != 0:
            jump = True
        elif self.jump == 6 and comp <= 0:
            jump = True
        elif self.jump == 7:
            jump = True

        if jump:
            return self.register_a.value
        else:
            return self.program_counter.value + 1

    @property
    def instruction(self):
        return self.rom[self.program_counter.value]

    @property
    def c_instruction(self):
        return (self.instruction & 0x8000) == 0x8000

    @property
    def from_ram(self):
        return (self.instruction & 0x1000) == 0x1000

    @property
    def op(self):
        return self.instruction & 0xFC0

    @property
    def dest(self):
        return self.instruction & 0x38

    @property
    def jump(self):
        return self.instruction & 0x7

    @property
    def store_m(self):
        return (self.dest & 0x8) == 0x8

    @property
    def store_d(self):
        return (self.dest & 0x10) == 0x10

    @property
    def store_a(self):
        return (self.dest & 0x20) == 0x20
Example #10
0
def whitebox(
        resetn,
        pclk,
        paddr,
        psel,
        penable,
        pwrite,
        pwdata,
        pready,
        prdata,
        #pslverr,
        clearn,
        clear_enable,
        dac_clock,
        dac2x_clock,
        dac_en,
        dac_data,
        adc_idata,
        adc_qdata,
        tx_status_led,
        tx_dmaready,
        rx_status_led,
        rx_dmaready,
        tx_fifo_re,
        tx_fifo_rdata,
        tx_fifo_we,
        tx_fifo_wdata,
        tx_fifo_full,
        tx_fifo_afull,
        tx_fifo_empty,
        tx_fifo_aempty,
        tx_fifo_afval,
        tx_fifo_aeval,
        tx_fifo_wack,
        tx_fifo_dvld,
        tx_fifo_overflow,
        tx_fifo_underflow,
        tx_fifo_rdcnt,
        tx_fifo_wrcnt,
        rx_fifo_re,
        rx_fifo_rdata,
        rx_fifo_we,
        rx_fifo_wdata,
        rx_fifo_full,
        rx_fifo_afull,
        rx_fifo_empty,
        rx_fifo_aempty,
        rx_fifo_afval,
        rx_fifo_aeval,
        rx_fifo_wack,
        rx_fifo_dvld,
        rx_fifo_overflow,
        rx_fifo_underflow,
        rx_fifo_rdcnt,
        rx_fifo_wrcnt,
        **kwargs):
    """The whitebox.

    :param resetn: Reset the whole radio front end.
    :param clearn: Clear the DSP Chain
    :param dac_clock: Clock running at DAC rate
    :param dac2x_clock: Clock running at double DAC rate
    :param pclk: The system bus clock
    :param paddr: The bus assdress
    :param psel: The bus slave select
    :param penable: The bus slave enable line
    :param pwrite: The bus read/write flag
    :param pwdata: The bus write data
    :param pready: The bus slave ready signal
    :param prdata: The bus read data
    :param pslverr: The bus slave error flag
    :param dac_clock: The DAC clock
    :param dac_data: The DAC data
    :param dac_en: Enable DAC output
    :param status_led: Output pin for whitebox status
    :param dmaready: Ready signal to DMA controller
    :param txirq: Almost empty interrupt to CPU
    :param clear_enable: To reset controller, set this high for reset
    """
    dspsim = kwargs.get('dspsim', None)
    interp_default = kwargs.get('interp', 1)
    fcw_bitwidth = kwargs.get('fcw_bitwidth', 25)

    ######### VARS AND FLAGS ###########
    print 'interp=', interp_default

    interp = Signal(intbv(interp_default)[11:])
    shift = Signal(intbv(0, min=0, max=21))
    firen = Signal(bool(0))
    fir_bank1 = Signal(bool(0))
    fir_bank0 = Signal(bool(0))
    fir_N = Signal(intbv(0, min=0, max=2**7))

    tx_correct_i = Signal(intbv(0, min=-2**9, max=2**9))
    tx_correct_q = Signal(intbv(0, min=-2**9, max=2**9))
    tx_gain_i = Signal(intbv(int(1.0 * 2**9 + .5))[10:])
    tx_gain_q = Signal(intbv(int(1.0 * 2**9 + .5))[10:])
    fcw = Signal(intbv(1)[fcw_bitwidth:])
    txen = Signal(bool(0))
    txstop = Signal(bool(0))
    txfilteren = Signal(bool(0))
    ddsen = Signal(bool(False))
    loopen = Signal(bool(False))

    decim = Signal(intbv(interp_default)[11:])
    rx_correct_i = Signal(intbv(0, min=-2**9, max=2**9))
    rx_correct_q = Signal(intbv(0, min=-2**9, max=2**9))
    rxen = Signal(bool(0))
    rxstop = Signal(bool(0))
    rxfilteren = Signal(bool(0))

    # The RAMs
    fir_coeff_ram = Ram(clearn, dac_clock, bus.pclk, width=18, depth=512)
    fir_delay_line_i_ram = Ram(clearn,
                               dac_clock,
                               dac_clock,
                               width=9,
                               depth=512)
    fir_delay_line_q_ram = Ram(clearn,
                               dac_clock,
                               dac_clock,
                               width=9,
                               depth=512)

    fir_coeff_ram_addr = fir_coeff_ram.port['a'].addr
    fir_coeff_ram_din = fir_coeff_ram.port['a'].din
    fir_coeff_ram_blk = fir_coeff_ram.port['a'].blk
    fir_coeff_ram_wen = fir_coeff_ram.port['a'].wen
    fir_coeff_ram_dout = fir_coeff_ram.port['a'].dout
    fir_load_coeff_ram_addr = fir_coeff_ram.port['b'].addr
    fir_load_coeff_ram_din = fir_coeff_ram.port['b'].din
    fir_load_coeff_ram_blk = fir_coeff_ram.port['b'].blk
    fir_load_coeff_ram_wen = fir_coeff_ram.port['b'].wen
    fir_load_coeff_ram_dout = fir_coeff_ram.port['b'].dout
    fir_delay_line_i_ram_addr = fir_delay_line_i_ram.port['a'].addr
    fir_delay_line_i_ram_din = fir_delay_line_i_ram.port['a'].din
    fir_delay_line_i_ram_blk = fir_delay_line_i_ram.port['a'].blk
    fir_delay_line_i_ram_wen = fir_delay_line_i_ram.port['a'].wen
    fir_delay_line_i_ram_dout = fir_delay_line_i_ram.port['a'].dout
    fir_delay_line_q_ram_addr = fir_delay_line_q_ram.port['a'].addr
    fir_delay_line_q_ram_din = fir_delay_line_q_ram.port['a'].din
    fir_delay_line_q_ram_blk = fir_delay_line_q_ram.port['a'].blk
    fir_delay_line_q_ram_wen = fir_delay_line_q_ram.port['a'].wen
    fir_delay_line_q_ram_dout = fir_delay_line_q_ram.port['a'].dout

    ########### DIGITAL SIGNAL PROCESSING #######
    loopback = Signature("loopback", False, bits=10)
    duc_underrun = Signal(modbv(0, min=0, max=2**16))
    dac_last = Signal(bool(0))

    ddc_overrun = Signal(modbv(0, min=0, max=2**16))
    ddc_flags = Signal(intbv(0)[4:])
    adc_last = Signal(bool(0))

    tx_sample = Signature("tx_sample", True, bits=16)
    tx_sample_valid = tx_sample.valid
    tx_sample_last = tx_sample.last
    tx_sample_i = tx_sample.i
    tx_sample_q = tx_sample.q

    rx_sample = Signature("rx_sample", True, bits=16)
    rx_sample_valid = rx_sample.valid
    rx_sample_last = rx_sample.last
    rx_sample_i = rx_sample.i
    rx_sample_q = rx_sample.q

    duc_args = (
        clearn,
        dac_clock,
        dac2x_clock,
        loopen,
        loopback,
        tx_fifo_empty,
        tx_fifo_re,
        tx_fifo_dvld,
        tx_fifo_rdata,
        tx_fifo_underflow,
        txen,
        txstop,
        ddsen,
        txfilteren,
        interp,
        shift,
        fcw,
        tx_correct_i,
        tx_correct_q,
        tx_gain_i,
        tx_gain_q,
        duc_underrun,
        tx_sample,
        dac_en,
        dac_data,
        dac_last,
        rx_fifo_full,
        rx_fifo_we,
        rx_fifo_wdata,
        rxen,
        rxstop,
        rxfilteren,
        decim,
        rx_correct_i,
        rx_correct_q,
        ddc_overrun,
        rx_sample,
        adc_idata,
        adc_qdata,
        adc_last,
        fir_coeff_ram_addr,
        fir_coeff_ram_din,
        fir_coeff_ram_blk,
        fir_coeff_ram_wen,
        fir_coeff_ram_dout,
        fir_delay_line_i_ram_addr,
        fir_delay_line_i_ram_din,
        fir_delay_line_i_ram_blk,
        fir_delay_line_i_ram_wen,
        fir_delay_line_i_ram_dout,
        fir_delay_line_q_ram_addr,
        fir_delay_line_q_ram_din,
        fir_delay_line_q_ram_blk,
        fir_delay_line_q_ram_wen,
        fir_delay_line_q_ram_dout,
        firen,
        fir_bank1,
        fir_bank0,
        fir_N,
    )

    duc_kwargs = dict(dspsim=dspsim,
                      interp=interp_default,
                      cic_enable=kwargs.get('cic_enable', True),
                      cic_order=kwargs.get('cic_order', 4),
                      cic_delay=kwargs.get('cic_delay', 1),
                      fir_enable=kwargs.get('fir_enable', True),
                      dds_enable=kwargs.get('dds_enable', True),
                      conditioning_enable=kwargs.get('conditioning_enable',
                                                     True))
    if kwargs.get("duc_enable", True):
        duc = DUC(*duc_args, **duc_kwargs)
    else:
        duc = None

    ########### RADIO FRONT END ##############
    rfe_args = (
        resetn,
        pclk,
        paddr,
        psel,
        penable,
        pwrite,
        pwdata,
        pready,
        prdata,  #pslverr,
        clearn,
        clear_enable,
        loopen,
        tx_status_led,
        tx_dmaready,
        rx_status_led,
        rx_dmaready,
        tx_fifo_we,
        tx_fifo_wdata,
        tx_fifo_empty,
        tx_fifo_full,
        tx_fifo_afval,
        tx_fifo_aeval,
        tx_fifo_afull,
        tx_fifo_aempty,
        tx_fifo_wack,
        tx_fifo_dvld,
        tx_fifo_overflow,
        tx_fifo_underflow,
        tx_fifo_rdcnt,
        tx_fifo_wrcnt,
        rx_fifo_re,
        rx_fifo_rdata,
        rx_fifo_empty,
        rx_fifo_full,
        rx_fifo_afval,
        rx_fifo_aeval,
        rx_fifo_afull,
        rx_fifo_aempty,
        rx_fifo_wack,
        rx_fifo_dvld,
        rx_fifo_overflow,
        rx_fifo_underflow,
        rx_fifo_rdcnt,
        rx_fifo_wrcnt,
        fir_load_coeff_ram_addr,
        fir_load_coeff_ram_din,
        fir_load_coeff_ram_blk,
        fir_load_coeff_ram_wen,
        fir_load_coeff_ram_dout,
        firen,
        fir_bank1,
        fir_bank0,
        fir_N,
        interp,
        shift,
        fcw,
        tx_correct_i,
        tx_correct_q,
        tx_gain_i,
        tx_gain_q,
        txen,
        txstop,
        ddsen,
        txfilteren,
        decim,
        rx_correct_i,
        rx_correct_q,
        rxen,
        rxstop,
        rxfilteren,
        duc_underrun,
        dac_last,
        ddc_overrun,
        adc_last)

    rfe = RFE(*rfe_args)

    instances = (rfe, duc)

    if kwargs.get('fir_enable', True):
        fir_coeff_ram_inst = fir_coeff_ram.instance_type()(
            **fir_coeff_ram.instance_signals())
        fir_delay_line_i_ram_inst = fir_delay_line_i_ram.instance_type()(
            **fir_delay_line_i_ram.instance_signals())
        fir_delay_line_q_ram_inst = fir_delay_line_q_ram.instance_type()(
            **fir_delay_line_q_ram.instance_signals())
        instances += (fir_coeff_ram_inst, fir_delay_line_i_ram_inst,
                      fir_delay_line_q_ram_inst)

    return instances
Example #11
0
 def __init__(self, data=None, fromq=None, toq=None):
     self.ram = Ram(32768, fromq, toq)
     self.rom = Rom(32768, data=data)
     self.register_a = Register()
     self.register_d = Register()
     self.program_counter = Register()
Example #12
0
 def __init__(self):
     self.__cpu = Cpu()
     self.__ram = Ram()
def init(cont):
    ram = Ram(cont.owner)
    ram.setState(WanderState(ram))
    cont.owner['initialized'] = True
Example #14
0
from zero import Zero
from cessna import Cessna
from ram import Ram
from tesla import Tesla

fxs = Zero()
fxs.main_color = "red"
fxs.drive()
fxs.turn("right")
fxs.stop()

modelS = Tesla()
modelS.main_color = "green"
modelS.drive()
modelS.turn("left")
modelS.stop()

mx410 = Cessna()
mx410.main_color = "white"
mx410.drive()
mx410.turn("right")
mx410.stop()

ram1500 = Ram()
ram1500.main_color = "orange"
ram1500.drive()
ram1500.turn("left")
ram1500.stop()
Example #15
0
    def test_fir_impulse(self):
        in_sign = Signature("in", True, bits=9)
        out_sign = Signature("out", True, bits=9)

        s = FirSim(in_sign=in_sign, out_sign=out_sign)
        #s.design(48e3, 6e3, 1e3, 40.0)
        taps = (4 << COEFF_SHIFT, 3 << COEFF_SHIFT, 2 << COEFF_SHIFT, 1 << COEFF_SHIFT)
        coeff_ram = Ram(s.clearn, s.clock, s.clock, data=taps,
            width=18, depth=512)
        delay_line_i_ram = Ram(s.clearn, s.clock, s.clock, width=9, depth=512)
        delay_line_q_ram = Ram(s.clearn, s.clock, s.clock, width=9, depth=512)
        enable = Signal(bool(1))
        bank1 = Signal(bool(0))
        bank0 = Signal(bool(0))
        N = Signal(intbv(4, min=0, max=2**7-1))

        coeff_ram_inst = coeff_ram.instance_type()(**coeff_ram.instance_signals())
        delay_line_i_ram_inst = delay_line_i_ram.instance_type()(**delay_line_i_ram.instance_signals())
        delay_line_q_ram_inst = delay_line_q_ram.instance_type()(**delay_line_q_ram.instance_signals())


        def test_fir_impulse():
            load_coeff_ram_addr = coeff_ram.port['b'].addr
            load_coeff_ram_blk = coeff_ram.port['b'].blk
            load_coeff_ram_wen = coeff_ram.port['b'].wen
            fir_0 = fir(s.clearn, s.clock, s.input, s.output,
                    coeff_ram.port['a'].addr,
                    coeff_ram.port['a'].din,
                    coeff_ram.port['a'].blk,
                    coeff_ram.port['a'].wen,
                    coeff_ram.port['a'].dout,
                    delay_line_i_ram.port['a'].addr,
                    delay_line_i_ram.port['a'].din,
                    delay_line_i_ram.port['a'].blk,
                    delay_line_i_ram.port['a'].wen,
                    delay_line_i_ram.port['a'].dout,
                    delay_line_q_ram.port['a'].addr,
                    delay_line_q_ram.port['a'].din,
                    delay_line_q_ram.port['a'].blk,
                    delay_line_q_ram.port['a'].wen,
                    delay_line_q_ram.port['a'].dout,
                    enable, bank1, bank0, N,
                    sim=s)

            return fir_0, coeff_ram_inst, delay_line_i_ram_inst, delay_line_q_ram_inst

        in_t = arange(0, 8)

        in_c = 0*in_t + 1j * 0*in_t
        in_i = 0*in_t
        in_q = 0*in_t
        in_i[0] = 1 << 5
        in_i[4] = 1 << 5

        out_i, out_q = s.simulate(in_i, in_q, test_fir_impulse, 128,
                coeff_ram, taps)
        out_t = arange(0, out_i.shape[0])

        new_shape = tuple([in_t.shape[i] for i in range(len(in_t.shape))])
        assert out_t.shape == new_shape
        print 'out_i', out_i
        assert array_equal(out_i, [4, 3, 2, 1, 4, 3, 2, 1])
Example #16
0
from leaf import Leaf
from crosstrek import CrossTrek
from mustang import Mustang
from ram import Ram
from pumpstation import PumpStation
from chargingstation import ChargingStation

ram = Ram()
must = Mustang()
tree = Leaf()

gas_pump_station = PumpStation()
electric_charging_station = ChargingStation()

gas_pump_station.add_vehicle(ram)
gas_pump_station.add_vehicle(must)
electric_charging_station.add_vehicle(tree)
Example #17
0
import threading, time, sys, signal
import configreader, harddisk_interface, tools

from ram import Ram
from constants import IS
from register import RegisterSet

config = configreader.getconfig()

cores = []
corenum = 0

ram = Ram(config["ram-size"])
try:
    hdd = harddisk_interface.HDD(sys.argv[1])
except IndexError:
    hdd = harddisk_interface.HDD("disk.hdd")
# vram = Ram(config["vram_size"])


class core(threading.Thread):
    def __init__(self, speed):
        super().__init__()
        self._stop_event = threading.Event()
        # self.daemon = True

        from status import STATUS
        self.STATUS = STATUS
        self.speed = speed

        self.enabled = True
from tesla import Tesla
from ram import Ram
from cessna import Cessna
from zero import Zero
# my_tesla = Tesla()

# my_tesla.main_color = "blue"

# print(my_tesla.main_color)

fxs = Zero()
modelS = Tesla()
mx410 = Cessna()
dodgeRam = Ram()

fxs.drive()
modelS.drive()
mx410.drive()
dodgeRam.drive()
Example #19
0
def whitebox(
        resetn,
        pclk,
        paddr,
        psel,
        penable,
        pwrite,
        pwdata,
        pready,
        prdata,
        #pslverr,
        clearn,
        clear_enable,
        dac_clock,
        dac2x_clock,
        dac_en,
        dac_data,
        adc_idata,
        adc_qdata,
        tx_status_led,
        tx_dmaready,
        rx_status_led,
        rx_dmaready,
        tx_fifo_re,
        tx_fifo_rdata,
        tx_fifo_we,
        tx_fifo_wdata,
        tx_fifo_full,
        tx_fifo_afull,
        tx_fifo_empty,
        tx_fifo_aempty,
        tx_fifo_afval,
        tx_fifo_aeval,
        tx_fifo_wack,
        tx_fifo_dvld,
        tx_fifo_overflow,
        tx_fifo_underflow,
        tx_fifo_rdcnt,
        tx_fifo_wrcnt,
        rx_fifo_re,
        rx_fifo_rdata,
        rx_fifo_we,
        rx_fifo_wdata,
        rx_fifo_full,
        rx_fifo_afull,
        rx_fifo_empty,
        rx_fifo_aempty,
        rx_fifo_afval,
        rx_fifo_aeval,
        rx_fifo_wack,
        rx_fifo_dvld,
        rx_fifo_overflow,
        rx_fifo_underflow,
        rx_fifo_rdcnt,
        rx_fifo_wrcnt,
        **kwargs):
    """The whitebox.

    :param resetn: Reset the whole radio front end.
    :param clearn: Clear the DSP Chain
    :param dac_clock: Clock running at DAC rate
    :param dac2x_clock: Clock running at double DAC rate
    :param pclk: The system bus clock
    :param paddr: The bus assdress
    :param psel: The bus slave select
    :param penable: The bus slave enable line
    :param pwrite: The bus read/write flag
    :param pwdata: The bus write data
    :param pready: The bus slave ready signal
    :param prdata: The bus read data
    :param pslverr: The bus slave error flag
    :param dac_clock: The DAC clock
    :param dac_data: The DAC data
    :param dac_en: Enable DAC output
    :param status_led: Output pin for whitebox status
    :param dmaready: Ready signal to DMA controller
    :param txirq: Almost empty interrupt to CPU
    :param clear_enable: To reset controller, set this high for reset
    """
    dspsim = kwargs.get('dspsim', None)
    interp_default = kwargs.get('interp', 1)
    fcw_bitwidth = kwargs.get('fcw_bitwidth', 25)

    ######### VARS AND FLAGS ###########
    print 'interp=', interp_default

    interp = Signal(intbv(interp_default)[11:])
    shift = Signal(intbv(0, min=0, max=21))
    firen = Signal(bool(0))
    fir_bank1 = Signal(bool(0))
    fir_bank0 = Signal(bool(0))
    fir_N = Signal(intbv(0, min=0, max=2**7))

    tx_correct_i = Signal(intbv(0, min=-2**9, max=2**9))
    tx_correct_q = Signal(intbv(0, min=-2**9, max=2**9))
    tx_gain_i = Signal(intbv(int(1.0 * 2**9 + .5))[10:])
    tx_gain_q = Signal(intbv(int(1.0 * 2**9 + .5))[10:])
    fcw = Signal(intbv(1)[fcw_bitwidth:])
    txen = Signal(bool(0))
    txstop = Signal(bool(0))
    txfilteren = Signal(bool(0))
    ddsen = Signal(bool(False))
    loopen = Signal(bool(False))

    decim = Signal(intbv(interp_default)[11:])
    rx_correct_i = Signal(intbv(0, min=-2**9, max=2**9))
    rx_correct_q = Signal(intbv(0, min=-2**9, max=2**9))
    rxen = Signal(bool(0))
    rxstop = Signal(bool(0))
    rxfilteren = Signal(bool(0))

    # The RAMs
    fir_coeff_ram = Ram(clearn, dac_clock, bus.pclk, width=18, depth=512)
    fir_delay_line_i_ram = Ram(clearn, dac_clock, dac_clock, width=9, depth=512)
    fir_delay_line_q_ram = Ram(clearn, dac_clock, dac_clock, width=9, depth=512)

    fir_coeff_ram_addr = fir_coeff_ram.port['a'].addr
    fir_coeff_ram_din = fir_coeff_ram.port['a'].din
    fir_coeff_ram_blk = fir_coeff_ram.port['a'].blk
    fir_coeff_ram_wen = fir_coeff_ram.port['a'].wen
    fir_coeff_ram_dout = fir_coeff_ram.port['a'].dout
    fir_load_coeff_ram_addr = fir_coeff_ram.port['b'].addr
    fir_load_coeff_ram_din = fir_coeff_ram.port['b'].din
    fir_load_coeff_ram_blk = fir_coeff_ram.port['b'].blk
    fir_load_coeff_ram_wen = fir_coeff_ram.port['b'].wen
    fir_load_coeff_ram_dout = fir_coeff_ram.port['b'].dout
    fir_delay_line_i_ram_addr = fir_delay_line_i_ram.port['a'].addr
    fir_delay_line_i_ram_din = fir_delay_line_i_ram.port['a'].din
    fir_delay_line_i_ram_blk = fir_delay_line_i_ram.port['a'].blk
    fir_delay_line_i_ram_wen = fir_delay_line_i_ram.port['a'].wen
    fir_delay_line_i_ram_dout = fir_delay_line_i_ram.port['a'].dout
    fir_delay_line_q_ram_addr = fir_delay_line_q_ram.port['a'].addr
    fir_delay_line_q_ram_din = fir_delay_line_q_ram.port['a'].din
    fir_delay_line_q_ram_blk = fir_delay_line_q_ram.port['a'].blk
    fir_delay_line_q_ram_wen = fir_delay_line_q_ram.port['a'].wen
    fir_delay_line_q_ram_dout = fir_delay_line_q_ram.port['a'].dout

    ########### DIGITAL SIGNAL PROCESSING #######
    loopback = Signature("loopback", False, bits=10)
    duc_underrun = Signal(modbv(0, min=0, max=2**16))
    dac_last = Signal(bool(0))

    ddc_overrun = Signal(modbv(0, min=0, max=2**16))
    ddc_flags = Signal(intbv(0)[4:])
    adc_last = Signal(bool(0))

    tx_sample = Signature("tx_sample", True, bits=16)
    tx_sample_valid = tx_sample.valid
    tx_sample_last = tx_sample.last
    tx_sample_i = tx_sample.i
    tx_sample_q = tx_sample.q

    rx_sample = Signature("rx_sample", True, bits=16)
    rx_sample_valid = rx_sample.valid
    rx_sample_last = rx_sample.last
    rx_sample_i = rx_sample.i
    rx_sample_q = rx_sample.q

    duc_args = (clearn, dac_clock, dac2x_clock,
            loopen, loopback,
            tx_fifo_empty, tx_fifo_re, tx_fifo_dvld, tx_fifo_rdata, tx_fifo_underflow,
            txen, txstop,
            ddsen, txfilteren,
            interp, shift,
            fcw,
            tx_correct_i, tx_correct_q,
            tx_gain_i, tx_gain_q,
            duc_underrun, tx_sample,
            dac_en, dac_data, dac_last,

            rx_fifo_full, rx_fifo_we, rx_fifo_wdata,
            rxen, rxstop, rxfilteren,
            decim, rx_correct_i, rx_correct_q,
            ddc_overrun, rx_sample,
            adc_idata, adc_qdata, adc_last,

            fir_coeff_ram_addr,
            fir_coeff_ram_din,
            fir_coeff_ram_blk,
            fir_coeff_ram_wen,
            fir_coeff_ram_dout,
            fir_delay_line_i_ram_addr,
            fir_delay_line_i_ram_din,
            fir_delay_line_i_ram_blk,
            fir_delay_line_i_ram_wen,
            fir_delay_line_i_ram_dout,
            fir_delay_line_q_ram_addr,
            fir_delay_line_q_ram_din,
            fir_delay_line_q_ram_blk,
            fir_delay_line_q_ram_wen,
            fir_delay_line_q_ram_dout,
            firen, fir_bank1, fir_bank0, fir_N,)

    duc_kwargs = dict(dspsim=dspsim,
                    interp=interp_default,
                    cic_enable=kwargs.get('cic_enable', True),
                    cic_order=kwargs.get('cic_order', 4),
                    cic_delay=kwargs.get('cic_delay', 1),
                    fir_enable=kwargs.get('fir_enable', True),
                    dds_enable=kwargs.get('dds_enable', True),
                    conditioning_enable=kwargs.get('conditioning_enable', True))
    if kwargs.get("duc_enable", True):
        duc = DUC(*duc_args, **duc_kwargs)
    else:
        duc = None

    ########### RADIO FRONT END ##############
    rfe_args = (resetn,
        pclk, paddr, psel, penable, pwrite, pwdata, pready, prdata, #pslverr,
        clearn, clear_enable, loopen,

        tx_status_led, tx_dmaready,
        rx_status_led, rx_dmaready,
        tx_fifo_we, tx_fifo_wdata,
        tx_fifo_empty, tx_fifo_full,
        tx_fifo_afval, tx_fifo_aeval, tx_fifo_afull, tx_fifo_aempty,
        tx_fifo_wack, tx_fifo_dvld,
        tx_fifo_overflow, tx_fifo_underflow,
        tx_fifo_rdcnt, tx_fifo_wrcnt,

        rx_fifo_re, rx_fifo_rdata,
        rx_fifo_empty, rx_fifo_full,
        rx_fifo_afval, rx_fifo_aeval, rx_fifo_afull, rx_fifo_aempty,
        rx_fifo_wack, rx_fifo_dvld,
        rx_fifo_overflow, rx_fifo_underflow,
        rx_fifo_rdcnt, rx_fifo_wrcnt,

        fir_load_coeff_ram_addr,
        fir_load_coeff_ram_din,
        fir_load_coeff_ram_blk,
        fir_load_coeff_ram_wen,
        fir_load_coeff_ram_dout,

        firen, fir_bank1, fir_bank0, fir_N,

        interp, shift,
        fcw, tx_correct_i, tx_correct_q, tx_gain_i, tx_gain_q,
        txen, txstop, ddsen, txfilteren,
        decim, rx_correct_i, rx_correct_q,
        rxen, rxstop, rxfilteren,
        duc_underrun, dac_last,
        ddc_overrun, adc_last)

    rfe = RFE(*rfe_args)

    instances = (rfe, duc)

    if kwargs.get('fir_enable', True):
        fir_coeff_ram_inst = fir_coeff_ram.instance_type()(**fir_coeff_ram.instance_signals())
        fir_delay_line_i_ram_inst = fir_delay_line_i_ram.instance_type()(**fir_delay_line_i_ram.instance_signals())
        fir_delay_line_q_ram_inst = fir_delay_line_q_ram.instance_type()(**fir_delay_line_q_ram.instance_signals())
        instances += (fir_coeff_ram_inst, fir_delay_line_i_ram_inst, fir_delay_line_q_ram_inst)


    return instances