def DIV(i): (l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2) register.storereg('edx') register.storereg('eax') datafile.blockout.append("xor edx, edx") try : int(z) reg = register.emptyregister(i,['edx', 'eax']) datafile.blockout.append('mov ' + reg + ", " + z) datafile.zprime = reg except : if datafile.addressdescriptor[z] == None: reg = register.emptyregister(i,['edx', 'eax']) datafile.blockout.append('mov ' + reg + ", " + register.mem(z)) datafile.zprime = reg try : int(y) datafile.yprime = "eax" datafile.blockout.append("mov eax," + y) except : datafile.blockout.append("mov eax," + register.mem(y)) datafile.yprime = "eax" datafile.L = "eax" datafile.blockout.append("idiv " +reg) register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)
def DIV(i): (l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2) register.storereg('edx') datafile.blockout.append("xor %edx, %edx") datafile.lineno = datafile.lineno + 1 try : int(z) reg = register.emptyregister(i,['edx', 'eax']) datafile.blockout.append('mov $' + z + ", %" + reg) datafile.lineno = datafile.lineno + 1 datafile.zprime = reg except : if datafile.addressdescriptor[z] == 'eax': register.storereg(z) register.getz(z) pass register.getreg(l, y, i, 'eax') try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("idivl " + register.mem(datafile.zprime)) datafile.lineno = datafile.lineno + 1 register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)
def MUL(i): (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out) datafile.zprime = z register.storereg("edx") try: int(z) datafile.blockout.append("mov edx," + register.mem(datafile.zprime)) except: if datafile.addressdescriptor[z] != None: datafile.blockout.append("mov edx," + datafile.addressdescriptor[z]) else: datafile.blockout.append("mov edx," + register.mem(datafile.zprime)) datafile.yprime = y register.storereg("eax") try: int(y) datafile.blockout.append("mov eax," + register.mem(datafile.yprime)) except: if datafile.addressdescriptor[y] != None: datafile.blockout.append("mov eax," + datafile.addressdescriptor[y]) else: datafile.blockout.append("mov eax," + register.mem(datafile.yprime)) datafile.blockout.append("imul edx") datafile.addressdescriptor[l] = "eax" datafile.registerdescriptor["eax"] = l register.freereg(y, i) register.freereg(z, i)
def COMPARE(i): (y,z) = (datafile.block[i].op1,datafile.block[i].op2) try: int(z) datafile.zprime = z except: datafile.zprime = register.getz(z) try: int(y) datafile.yprime = y except: if datafile.addressdescriptor[y] != None: datafile.L = datafile.addressdescriptor[y] elif datafile.zprime in datafile.allvariables: reg = register.emptyregister(i) datafile.blockout.append("movl " + register.mem(y) + ", " + register.mem(reg)) datafile.lineno = datafile.lineno + 1 datafile.L = reg datafile.registerdescriptor[reg] = y datafile.addressdescriptor[y] = reg else: datafile.L = y datafile.blockout.append("cmp " + register.mem(y) + ", " + register.mem(z)) datafile.lineno = datafile.lineno + 1 register.freereg(y,i) register.freereg(z,i)
def ADD(i): (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out) #check if z is constant or not if not get the momloc or register if it is already in register since op r_i , r_j is similar to op r_i , M print y,", ", z, ", ", l ,"these are y and l in add function" try : int(z) datafile.zprime = z except : register.getz(z) pass #get the register for L to store the output of the operation register.getreg(l, y, i) # print datafile.L , "Hello" try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("addl " + register.mem(datafile.zprime) + ", " + register.mem(datafile.L)) # datafile.blockout.append("lineno" + str(datafile.lineno)) datafile.lineno = datafile.lineno + 1 register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)
def ASSIGN(i): (y,l) = (datafile.block[i].op2,datafile.block[i].out) register.getreg(l,y,i) try : int(y) datafile.yprime = y except : pass register.gety(y) register.UpdateAddressDescriptor(l) register.freereg(y, i)
def ADD(i): (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out) try : int(z) datafile.zprime = z except : register.getz(z) pass register.getreg(l, y, i) try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("add " + register.mem(datafile.L) + ", "+register.mem(datafile.zprime) ) datafile.lineno = datafile.lineno + 1 register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)
def XOR(i): (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out) #check if z is constant or not if not get the momloc or register if it is already in register since op r_i , r_j is similar to op r_i , M try : int(z) datafile.zprime = z except : register.getz(z) pass #get the register for L to store the output of the operation register.getreg(l, y, i) try : int(y) datafile.yprime = y except : pass register.gety(y) datafile.blockout.append("xor " + register.mem(datafile.L) + ", " + register.mem(datafile.zprime) ) datafile.lineno = datafile.lineno + 1 register.UpdateAddressDescriptor(l) register.freereg(y, i) register.freereg(z, i)
def COMPARE(i): (y,z) = (datafile.block[i].op1,datafile.block[i].op2) try: int(z) datafile.zprime = z except: register.getz(z) try: int(y) datafile.yprime = y reg = register.emptyregister(i,[datafile.zprime]) datafile.blockout.append("mov " + reg + "," + datafile.yprime) datafile.yprime = reg except: if datafile.addressdescriptor[y] != None: datafile.L = datafile.addressdescriptor[y] datafile.yprime = datafile.addressdescriptor[y] elif datafile.zprime in datafile.allvariables: reg = register.emptyregister(i) datafile.blockout.append("mov " + reg + ", " + register.mem(y) ) datafile.yprime = reg datafile.registerdescriptor[reg] = y datafile.addressdescriptor[y] = reg elif datafile.zprime not in datafile.registerlist: reg = register.emptyregister(i) datafile.blockout.append("mov " + reg + ", " + register.mem(y) ) datafile.yprime = reg datafile.registerdescriptor[reg] = y datafile.addressdescriptor[y] = reg if datafile.yprime in datafile.registerlist: datafile.blockout.append("cmp " + datafile.yprime + "," + register.mem(datafile.zprime)) else: datafile.blockout.append("cmp " + register.mem(datafile.yprime) + "," + datafile.zprime) register.freereg(y,i) register.freereg(z,i)
def DEFASSIGN(i): (y,l) = (datafile.block[i].op2,datafile.block[i].out) try : int(y) datafile.yprime = y if datafile.addressdescriptor[l] != None: reg = datafile.addressdescriptor[l] else: reg = register.emptyregister(i) datafile.L = reg register.UpdateAddressDescriptor(l) except : if datafile.addressdescriptor[y] != None: if datafile.addressdescriptor[l] != None: datafile.blockout.append("mov " + '['+datafile.addressdescriptor[l]+']' + "," + datafile.addressdescriptor[y]) register.freereg(y, i) return else: reg = register.emptyregister(i,left=[datafile.addressdescriptor[y]]) datafile.blockout.append('mov ' + reg + ',' + register.mem(l)) datafile.blockout.append("mov " + '['+reg+']' + "," + datafile.addressdescriptor[y]) register.freereg(y, i) register.freereg(reg, i) return else: reg = register.emptyregister(i) # for l reg1 = register.emptyregister(i,[reg]) # for y datafile.blockout.append("mov " + reg1 + "," + register.mem(y)) datafile.L = reg if datafile.addressdescriptor[l] == None: datafile.blockout.append("mov " + reg + ", "+ register.mem(l)) else: datafile.blockout.append("mov " + reg + ", "+ datafile.addressdescriptor[l]) datafile.blockout.append("mov " + '['+reg+']' + "," + reg1) datafile.yprime = reg1 register.UpdateAddressDescriptor(l) register.freereg(y,i) register.freereg(reg1,i) return reg1 = register.emptyregister(i, [reg]) datafile.blockout.append("mov " + reg1 + "," + y) datafile.blockout.append("mov " + '['+reg+']' + "," + reg1) register.freereg(y, i) register.freereg(reg, i)