def fpgalink_nexys(
# ~~ FX2 interface signals ~~
IFCLK, # 48 MHz clock from FX2
RST, # active low async reset
SLWR, # active low write strobe
SLRD, # active low read strobe
SLOE, # active low output enable
FDI, # input data bus
FDO, # output data bus
FDS, # data select
ADDR, # 2bit address (fifo select)
FLAGA, # not used
FLAGB, # gotroom
FLAGC, # gotdata
FLAGD, # not used
PKTEND, # submit partial (less than 512)
# ~~ peripherals interfaces ~~
LEDS # external LEDs
):
"""
"""
# get the local references for the top-level
clock,reset,fx2_bus,fl_bus = fpgalink.get_interfaces()
clock = IFCLK
reset = RST
fx2_bus.data_i = FDI
fx2_bus.data_o = FDO
fx2_bus.data_t = FDS
fx2_bus.gotdata = FLAGC
fx2_bus.gotroom = FLAGB
fx2_bus.write = SLWR
fx2_bus.read = SLRD
# SLOE = SLRD now shadowed signals for conversion
fx2_bus.pktend = PKTEND
# instantiate the fpgalink interface
g_fli = m_fpgalink_fx2(clock, reset, fx2_bus, fl_bus)
# ~~~~~~
lreg = Signal(intbv(0)[7:])
treg = Signal(intbv(0)[1:])
tcnt = Signal(modbv(0, min=0, max=2**24))
# aliases
f2hValid_in = fl_bus.valid_i
h2fReady_in = fl_bus.ready_i
h2fValid_out = fl_bus.valid_o
chanAddr_out = fl_bus.chan_addr
f2hData_in = fl_bus.data_i
h2fData_out = fl_bus.data_o
fifosel = fx2_bus.fifosel
@always_comb
def hdl_assigns():
ADDR.next[0] = False
ADDR.next[1] = fifosel
SLOE.next = SLRD
f2hValid_in.next = True
h2fReady_in.next = True
LEDS.next[7:] = lreg
LEDS.next[7] = treg
if chanAddr_out == 0:
f2hData_in.next = 0xCE
elif chanAddr_out == 1:
f2hData_in.next = lreg
else:
f2hData_in.next = 0x55
@always_seq(clock.posedge, reset=reset)
def hdl_fl():
if h2fValid_out and chanAddr_out == 1:
lreg.next = h2fData_out
tcnt.next = tcnt + 1
if tcnt[23]:
treg.next = not treg
return g_fli, hdl_fl, hdl_assigns
def tb_fpgalink(args):
"""
flbus1 - MyHDL model
flbus2 - original fpgalink Verilog
flbus3 - MyHDL converted Verilog
"""
# Get the FX2 emulations / host API and busses
fl = FpgaLinkHost(verbose=True)
clock, reset, fx2bus1, flbus1 = fpgalink.get_interfaces()
c, r, fx2bus2, flbus2 = fpgalink.get_interfaces()
fx2ext = fl.get_bus() # get the FX2 bus
clock = fx2ext.IFCLK
reset = fx2ext.RST
# connect the buses
gm = map_ext_int(clock, reset, fx2ext, fx2bus1)
# only one model driving the bus, connect the buses
fx2bus2.data_i = fx2bus1.data_i
fx2bus2.gotdata = fx2bus1.gotdata
fx2bus2.gotroom = fx2bus1.gotroom
# get the two HDL versions (MyHDL and Verilog)
traceSignals.name = args.vcd
tb_dut = traceSignals(fpgalink_fx2, clock, reset, fx2bus1, flbus1)
tb_fl1 = m_fpga_logic_ex1(clock, reset, flbus1)
if args.cosim:
tb_cosim = flcosim(clock, reset, fx2bus2, flbus2)
tb_fl2 = m_fpga_logic_ex1(clock, reset, flbus2)
else:
tb_cosim = ()
tb_fl2 = ()
g = (tb_dut, tb_cosim, tb_fl1, tb_fl2, gm)
# Start up the simulation using the FpgaLinkHost
fl.setup(fx2ext, g=g) # setup the simulation
fl.start() # start the simulation
assert fx2bus1.data_i is fx2ext.FDO
# ~~~~~~~~~~~~~~~
# Test stimulus
fl.reset()
assert fx2bus1.data_i is fx2ext.FDO
fl.write_channel(1, [9])
fl.write_channel(2, [8])
fl.write_channel(3, [7])
fl.write_channel(4, [6])
bb = [ii for ii in (0xFE, 0xED, 0xFA, 0xCE)]
bb[0] = fl.read_channel(1, 1)
bb[1] = fl.read_channel(2, 1)
bb[2] = fl.read_channel(3, 1)
bb[3] = fl.read_channel(4, 1)
print(bb)
# ~~~~~~~~~~~~~~~
# Stop simulation
fl.stop()
time.sleep(1)
def tb_fpgalink(args):
"""
flbus1 - MyHDL model
flbus2 - original fpgalink Verilog
flbus3 - MyHDL converted Verilog
"""
# Get the FX2 emulations / host API and busses
fl = FpgaLinkHost(verbose=True)
clock, reset, fx2bus1, flbus1 = fpgalink.get_interfaces()
c, r, fx2bus2, flbus2 = fpgalink.get_interfaces()
fx2ext = fl.get_bus() # get the FX2 bus
clock = fx2ext.IFCLK
reset = fx2ext.RST
# connect the buses
gm = map_ext_int(clock, reset, fx2ext, fx2bus1)
# only one model driving the bus, connect the buses
fx2bus2.data_i = fx2bus1.data_i
fx2bus2.gotdata = fx2bus1.gotdata
fx2bus2.gotroom = fx2bus1.gotroom
# get the two HDL versions (MyHDL and Verilog)
tb_dut = traceSignals(fpgalink_fx2, clock, reset, fx2bus1, flbus1)
tb_fl1 = m_fpga_logic_ex1(clock, reset, flbus1)
if args.cosim:
tb_cosim = flcosim(clock, reset, fx2bus2, flbus2)
tb_fl2 = m_fpga_logic_ex1(clock, reset, flbus2)
else:
tb_cosim = ()
tb_fl2 = ()
g = (tb_dut, tb_cosim, tb_fl1, tb_fl2, gm)
# Start up the simulation using the FpgaLinkHost
fl.setup(fx2ext, g=g) # setup the simulation
fl.start() # start the simulation
assert fx2bus1.data_i is fx2ext.FDO
# ~~~~~~~~~~~~~~~
# Test stimulus
fl.reset()
assert fx2bus1.data_i is fx2ext.FDO
fl.write_channel(1, [9])
fl.write_channel(2, [8])
fl.write_channel(3, [7])
fl.write_channel(4, [6])
bb = [ii for ii in (0xFE, 0xED, 0xFA, 0xCE)]
bb[0] = fl.read_channel(1, 1)
bb[1] = fl.read_channel(2, 1)
bb[2] = fl.read_channel(3, 1)
bb[3] = fl.read_channel(4, 1)
print(bb)
# ~~~~~~~~~~~~~~~
# Stop simulation
fl.stop()
time.sleep(1)
