def _parse_signal_sources(self): srcs = [] candidates = [] # This is internal clock source. for i, plug in self.subunit_plugs['music']['output'].items(): if plug['type'] == 'Sync': addr = AvcCcm.get_subunit_signal_addr('music', 0, i) candidates.append((addr, plug)) # External source is available. for i, plug in self.unit_plugs['external']['input'].items(): if plug['type'] in ('Sync', 'Digital', 'Clock'): addr = AvcCcm.get_unit_signal_addr('external', i) candidates.append((addr, plug)) # SYT-match is available, but not practical. for i, plug in self.unit_plugs['isoc']['input'].items(): if plug['type'] == 'Sync': addr = AvcCcm.get_unit_signal_addr('isoc', i) candidates.append((addr, plug)) # BeBoBv3 has. # Inquire these are able to connect to destination. for params in candidates: addr = params[0] plug = params[1] try: AvcCcm.ask_signal_source(self.fcp, addr, self.signal_destination) except: continue srcs.append(params) return srcs
def _parse_signal_sources(self, fcp): srcs = {} candidates = {} # This is internal clock source. for i, plug in enumerate(self.subunit_plugs['music']['output']): if plug['type'] == 'Sync': addr = AvcCcm.get_subunit_signal_addr('music', 0, i) candidates[plug['name']] = addr # External source is available. for i, plug in enumerate(self.unit_plugs['external']['input']): if plug['type'] in ('Sync', 'Digital', 'Clock'): addr = AvcCcm.get_unit_signal_addr('external', i) candidates[plug['name']] = addr # SYT-match is available, but not practical. for i, plug in enumerate(self.unit_plugs['isoc']['input']): if plug['type'] == 'Sync': addr = AvcCcm.get_unit_signal_addr('isoc', i) candidates[plug['name']] = addr # Inquire these are able to connect to destination. for key, src in candidates.items(): try: AvcCcm.ask_signal_source(fcp, src, self.signal_destination) except: continue srcs[key] = src return srcs
def _parse_signal_destination(self): dst = [] for i, plug in self.subunit_plugs['music']['input'].items(): if plug['type'] == 'Sync': dst = AvcCcm.get_subunit_signal_addr('music', 0, i) return dst
def get_clock_source(self): dst = AvcCcm.get_subunit_signal_addr('music', 0, 1) curr = AvcCcm.get_signal_source(self.fcp, dst) for name, addr in self._clocks[self._id].items(): if AvcCcm.compare_addrs(curr, AvcCcm.parse_signal_addr(addr)): return name
def set_clock_source(self, src): dst = AvcCcm.get_subunit_signal_addr('music', 0, 1) addr = self._clocks[self._id][src] AvcCcm.set_signal_source(self.fcp, addr, dst)
def _parse_signal_destination(self, fcp): dst = [] for i, plug in enumerate(self.subunit_plugs['music']['input']): if plug['type'] == 'Sync': dst = AvcCcm.get_subunit_signal_addr('music', 0, i) return dst
#!/usr/bin/env python3 from gi.repository import Hinawa from ta1394.general import AvcGeneral from ta1394.ccm import AvcCcm path = '/dev/fw{0}'.format(argv[1]) unit = Hinawa.FwUnit(path) unit.listen() fcp = Hinawa.FwFcp() fcp.listen(unit) clk_dst = AvcCcm.get_subunit_signal_addr('music', 0, 17) # Sync to cycle start packet in IEEE 1394 bus, generally OHCI 1394 # host controller generates the packet, thus in fact the device # synchronizes to cycle of the controller. clk_csp_src = AvcCcm.get_subunit_signal_addr('music', 0, 17) # Word clock input. clk_word_src = AvcCcm.get_unit_signal_addr('external', 17) # Some digital signals to optical interface. clk_opt_src = AvcCcm.get_unit_signal_addr('external', 18) # Retrieve current source curr_src = AvcCcm.get_signal_source(fcp, clk_dst) # The curr_src may be one of the above sources. # Check avail or not # If not, exception raises. AvcCcm.ask_signal_source(fcp, clk_csp_src)