def parseBinary(operand1, opStart): op = getBinOp(opStart) if not op: return None # not a binary operation # if "( (DLY_LANE0_IDELAY & 8'hff)" in line: # print("parseBinary(): %d(%d): %s"%(opStart,len(line),line[opStart:])) # if (opStart>530): # print ("(pre)Last one!") start2 = skipWS(opStart + len(op[0])) if (self.verbose > 2): print("line=%s" % line) print("opStart=%d, start2=%d" % (opStart, start2)) operand2 = parseExp(start2) if not operand2: print( "ERROR: Could not get the second operand for '%s' in '%s'" % (op[0], line)) return None width1 = getParWidth(operand1[1]) width2 = getParWidth(operand2[1]) if (self.verbose > 2): print("operand1=%s" % str(operand1)) print("operand2=%s" % str(operand2)) exp = op[1]((operand1[0], width1), (operand2[0], width2)) if (self.verbose > 2): print("exp=%s" % str(exp)) if not exp: print("ERROR: Failed '%s' in '%s'" % (op[0], line)) return None #Try limiting to 32 bits width = exp[1] if (width1 == 32) and (exp[1] > 32) and ((width >> 32) == 0): width = 32 return (exp[0], "[%d:0]" % (width - 1), operand2[2])
def parseBinary(operand1, opStart): op=getBinOp(opStart) if not op: return None # not a binary operation # if "( (DLY_LANE0_IDELAY & 8'hff)" in line: # print("parseBinary(): %d(%d): %s"%(opStart,len(line),line[opStart:])) # if (opStart>530): # print ("(pre)Last one!") start2=skipWS(opStart+len(op[0])) if (self.verbose>2): print ("line=%s"%line) print ("opStart=%d, start2=%d"%(opStart, start2)) operand2=parseExp(start2) if not operand2: print("ERROR: Could not get the second operand for '%s' in '%s'"%(op[0],line)) return None width1=getParWidth(operand1[1]) width2=getParWidth(operand2[1]) if (self.verbose>2): print("operand1=%s"%str(operand1)) print("operand2=%s"%str(operand2)) exp=op[1]((operand1[0],width1),(operand2[0],width2)) if (self.verbose>2): print("exp=%s"%str(exp)) if not exp: print("ERROR: Failed '%s' in '%s'"%(op[0],line)) return None #Try limiting to 32 bits width=exp[1] if (width1==32) and (exp[1]>32) and ((width >> 32) == 0): width=32 return (exp[0],"[%d:0]"%(width-1),operand2[2])
def axi_set_tristate_patterns(self, strPattern=None): """ Set sequencer patterns for the tristate ON/OFF (defined by parameters) <strPattern> - optional up to 4-letter pattern. Each letter is one of 3: 'E'- early, "N" - nominal and 'L' - late, first for DQ start, second - for DQS start, then DQ end and DQS end. If no pattern is provided, all will be set to Verilog parameter values (DQ*TRI_*), if only 1 - it will be applied to all, if 2 - it will be repeated twice, 3 will use the same value for DQS end as for DQS start """ modes={'E':0,'N':1,'L':2} evNames=('DQ_FIRST', 'DQS_FIRST', 'DQ_LAST','DQS_LAST') patVals={evNames[0]: (0x3,0x7,0xf), # DQ_FIRST: early, nominal, late evNames[1]: (0x1,0x3,0x7), # DQS_FIRST: early, nominal, late evNames[2]: (0xf,0xe,0xc), # DQ_LAST: early, nominal, late evNames[3]: (0xe,0xc,0x8)} # DQS_LAST: early, nominal, late if not strPattern: delays=concat(((0,16), # {16'h0, (vrlg.DQSTRI_LAST, getParWidth(vrlg.DQSTRI_LAST__TYPE)), # DQSTRI_LAST, (vrlg.DQSTRI_FIRST,getParWidth(vrlg.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST, (vrlg.DQTRI_LAST, getParWidth(vrlg.DQTRI_LAST__TYPE)), # DQTRI_LAST, (vrlg.DQTRI_FIRST, getParWidth(vrlg.DQTRI_FIRST__TYPE))) # DQTRI_FIRST}); )[0] else: strPattern=strPattern.upper() if len(strPattern) == 1: strPattern*=4 elif len(strPattern) == 2: strPattern*=2 elif len(strPattern) == 3: strPattern+=strPattern[1] strPattern=strPattern[:4] vals={} for i,n in enumerate(evNames): try: vals[n]=patVals[n][modes[strPattern[i]]] except: msg="axi_set_tristate_patterns(%s): Failed to determine delay mode for %s, got %s"%(strPattern,n,strPattern[i]) print (msg) Exception(msg) print ("axi_set_tristate_patterns(%s) : %s"%(strPattern,str(vals))) delays=concat(((0,16), # {16'h0, (vals['DQS_LAST'],4), # vrlg.DQSTRI_LAST, getParWidth(vrlg.DQSTRI_LAST__TYPE)), # DQSTRI_LAST, (vals['DQS_FIRST'],4), # vrlg.DQSTRI_FIRST,getParWidth(vrlg.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST, (vals['DQ_LAST'],4), # vrlg.DQTRI_LAST, getParWidth(vrlg.DQTRI_LAST__TYPE)), # DQTRI_LAST, (vals['DQ_FIRST'],4)) # vrlg.DQTRI_FIRST, getParWidth(vrlg.DQTRI_FIRST__TYPE))) # DQTRI_FIRST}); )[0] # may fail if some of the parameters used have undefined width print("DQTRI_FIRST=%s, DQTRI_FIRST__TYPE=%s"%(str(vrlg.DQTRI_FIRST),str(vrlg.DQTRI_FIRST__TYPE))) print("DQTRI_LAST=%s, DQTRI_LAST__TYPE=%s"%(str(vrlg.DQTRI_LAST),str(vrlg.DQTRI_LAST__TYPE))) if self.DEBUG_MODE > 1: print("SET TRISTATE PATTERNS, combined delays=%s"%str(delays)) print("SET TRISTATE PATTERNS, combined delays=0x%x"%delays) self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_16BIT_ADDR +vrlg.MCONTR_PHY_16BIT_PATTERNS_TRI, delays) # DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
def parseExp(start=0, topExpr=False): start = skipWS(start) if start >= len(line): print( "ERROR: EOL reached when expression was expected in '%s'" % line) return None # if "( (DLY_LANE0_IDELAY & 8'hff)" in line: # print (line) # if (line[0]=='(') and (start==0): # print("Line starts with '(") if (line[start] == '(') or topExpr: # if (line[start]=='('): if not topExpr: start += 1 exp = parseExp(start) if not exp: print( "ERROR: failed to evaluate expression in '%s' (starting from '%s'" % (line, line[start:])) return None while True: endPos = skipWS(exp[2]) if (endPos >= len(line)) and (not topExpr): print( "ERROR: EOL reached when closing ')' was expected in '%s'" % line) return None if (endPos >= len(line)) or ( line[endPos] == ")" ): # (endPos >= len(line)) can only be here if topExpr endPos = skipWS(endPos + 1) if (exp is None) or (exp[1] is None): print("line=%s" % (line)) print() # print ("exp=%s"%(str(exp))) if isinstance(exp[0], (int, long)): width = getParWidth(exp[1]) elif isinstance(exp[0], str): width = 8 * len(exp[0]) else: # width=0 # print ("Unrecognized width in %s"%(str(exp))) # print ("line=%s"%(line)) return (exp[0], exp[1], endPos) return (exp[0], "[%d:0]" % (width - 1), endPos) # here may be binOp binRes = parseBinary(exp, endPos) if not binRes: print("endPos=%d, len(line)=%d, exp=%s" % (endPos, len(line), str(exp))) raise Exception( "ERROR: Next token in '%s' (starting from '%s') is not a binary operation or closing')'" % (line, line[endPos:])) exp = binRes return parsePrimaryOrBinary(start)
def parseExp(start=0, topExpr=False): start=skipWS(start) if start>=len(line): print ("ERROR: EOL reached when expression was expected in '%s'"%line) return None # if "( (DLY_LANE0_IDELAY & 8'hff)" in line: # print (line) # if (line[0]=='(') and (start==0): # print("Line starts with '(") if (line[start]=='(') or topExpr: # if (line[start]=='('): if not topExpr: start+=1 exp=parseExp(start) if not exp: print ("ERROR: failed to evaluate expression in '%s' (starting from '%s'"%(line,line[start:])) return None while True: endPos=skipWS(exp[2]) if (endPos >= len(line)) and (not topExpr): print ("ERROR: EOL reached when closing ')' was expected in '%s'"%line) return None if (endPos >= len(line)) or (line[endPos] == ")"): # (endPos >= len(line)) can only be here if topExpr endPos=skipWS(endPos+1) if (exp is None) or (exp[1] is None): print ("line=%s"%(line)) print () # print ("exp=%s"%(str(exp))) if isinstance(exp[0],(int,long)): width=getParWidth(exp[1]) elif isinstance(exp[0],str): width=8*len(exp[0]) else: # width=0 # print ("Unrecognized width in %s"%(str(exp))) # print ("line=%s"%(line)) return (exp[0],exp[1],endPos) return (exp[0],"[%d:0]"%(width-1),endPos) # here may be binOp binRes=parseBinary(exp, endPos) if not binRes: print ("endPos=%d, len(line)=%d, exp=%s"%(endPos,len(line),str(exp))) raise Exception("ERROR: Next token in '%s' (starting from '%s') is not a binary operation or closing')'"% (line,line[endPos:])) exp=binRes return parsePrimaryOrBinary(start)
def axi_set_tristate_patterns(self, strPattern=None): """ Set sequencer patterns for the tristate ON/OFF (defined by parameters) <strPattern> - optional up to 4-letter pattern. Each letter is one of 3: 'E'- early, "N" - nominal and 'L' - late, first for DQ start, second - for DQS start, then DQ end and DQS end. If no pattern is provided, all will be set to Verilog parameter values (DQ*TRI_*), if only 1 - it will be applied to all, if 2 - it will be repeated twice, 3 will use the same value for DQS end as for DQS start """ modes = {'E': 0, 'N': 1, 'L': 2} evNames = ('DQ_FIRST', 'DQS_FIRST', 'DQ_LAST', 'DQS_LAST') patVals = { evNames[0]: (0x3, 0x7, 0xf), # DQ_FIRST: early, nominal, late evNames[1]: (0x1, 0x3, 0x7), # DQS_FIRST: early, nominal, late evNames[2]: (0xf, 0xe, 0xc), # DQ_LAST: early, nominal, late evNames[3]: (0xe, 0xc, 0x8) } # DQS_LAST: early, nominal, late if not strPattern: delays = concat(( (0, 16), # {16'h0, (vrlg.DQSTRI_LAST, getParWidth(vrlg.DQSTRI_LAST__TYPE)), # DQSTRI_LAST, (vrlg.DQSTRI_FIRST, getParWidth(vrlg.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST, (vrlg.DQTRI_LAST, getParWidth(vrlg.DQTRI_LAST__TYPE)), # DQTRI_LAST, (vrlg.DQTRI_FIRST, getParWidth(vrlg.DQTRI_FIRST__TYPE)) ) # DQTRI_FIRST}); )[0] else: strPattern = strPattern.upper() if len(strPattern) == 1: strPattern *= 4 elif len(strPattern) == 2: strPattern *= 2 elif len(strPattern) == 3: strPattern += strPattern[1] strPattern = strPattern[:4] vals = {} for i, n in enumerate(evNames): try: vals[n] = patVals[n][modes[strPattern[i]]] except: msg = "axi_set_tristate_patterns(%s): Failed to determine delay mode for %s, got %s" % ( strPattern, n, strPattern[i]) print(msg) Exception(msg) print("axi_set_tristate_patterns(%s) : %s" % (strPattern, str(vals))) delays = concat(( (0, 16), # {16'h0, ( vals['DQS_LAST'], 4 ), # vrlg.DQSTRI_LAST, getParWidth(vrlg.DQSTRI_LAST__TYPE)), # DQSTRI_LAST, ( vals['DQS_FIRST'], 4 ), # vrlg.DQSTRI_FIRST,getParWidth(vrlg.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST, ( vals['DQ_LAST'], 4 ), # vrlg.DQTRI_LAST, getParWidth(vrlg.DQTRI_LAST__TYPE)), # DQTRI_LAST, (vals['DQ_FIRST'], 4) ) # vrlg.DQTRI_FIRST, getParWidth(vrlg.DQTRI_FIRST__TYPE))) # DQTRI_FIRST}); )[0] # may fail if some of the parameters used have undefined width print("DQTRI_FIRST=%s, DQTRI_FIRST__TYPE=%s" % (str(vrlg.DQTRI_FIRST), str(vrlg.DQTRI_FIRST__TYPE))) print("DQTRI_LAST=%s, DQTRI_LAST__TYPE=%s" % (str(vrlg.DQTRI_LAST), str(vrlg.DQTRI_LAST__TYPE))) if self.DEBUG_MODE > 1: print("SET TRISTATE PATTERNS, combined delays=%s" % str(delays)) print("SET TRISTATE PATTERNS, combined delays=0x%x" % delays) self.x393_axi_tasks.write_control_register( vrlg.MCONTR_PHY_16BIT_ADDR + vrlg.MCONTR_PHY_16BIT_PATTERNS_TRI, delays) # DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});