def create_ui(self, test_patterns=None, persistent_sim=True):
vhdl_path = join(dirname(__file__), "vhdl")
ui = VUnit(verbose=True,
clean=True,
test_filter=make_test_filter(test_patterns),
output_path=self.output_path,
xunit_xml=self.report_file,
persistent_sim=persistent_sim)
ui.add_library("lib")
ui.add_source_files(join(vhdl_path, "*.vhd"), "lib")
return ui
def create_ui(self, test_patterns=None, persistent_sim=True):
vhdl_path = join(dirname(__file__), "vhdl")
ui = VUnit(verbose=True,
clean=True,
test_filter=make_test_filter(test_patterns),
output_path=self.output_path,
xunit_xml=self.report_file,
persistent_sim=persistent_sim)
ui.add_library("lib")
ui.add_source_files(join(vhdl_path, "*.vhd"), "lib")
return ui
def run_sim(self, vhdl_standard):
output_path = join(dirname(__file__), "run_out")
ui = VUnit(clean=True,
output_path=output_path,
vhdl_standard=vhdl_standard)
ui.add_library("tb_run_lib")
vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl', 'run')
ui.add_source_files(join(vhdl_path, 'test', '*.vhd'), "tb_run_lib")
try:
ui.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
def test_compile_verilog(self):
verilog_path = join(dirname(__file__), "verilog")
ui = VUnit(verbose=True,
clean=True,
output_path=self.output_path,
xunit_xml=self.report_file,
compile_only=True)
ui.add_library("lib")
ui.add_source_files(join(verilog_path, "*.v"), "lib")
ui.add_source_files(join(verilog_path, "*.sv"), "lib")
try:
ui.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
def run_sim(self, vhdl_standard):
output_path = join(dirname(abspath(__file__)), 'path_out')
vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl')
ui = VUnit(clean=True,
output_path=output_path,
vhdl_standard=vhdl_standard)
ui.add_library("lib")
ui.add_source_files(join(vhdl_path, "path", "test", "*.vhd"), "lib")
try:
ui.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
def run_sim(self, vhdl_standard):
output_path = join(dirname(abspath(__file__)), 'path_out')
vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl')
ui = VUnit(clean=True,
output_path=output_path,
vhdl_standard=vhdl_standard)
ui.add_library("lib")
ui.add_source_files(join(vhdl_path, "path", "test", "*.vhd"), "lib")
try:
ui.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
def test_compile_verilog(self):
verilog_path = join(dirname(__file__), "verilog")
ui = VUnit(verbose=True,
clean=True,
output_path=self.output_path,
xunit_xml=self.report_file,
compile_only=True)
ui.add_library("lib")
ui.add_source_files(join(verilog_path, "*.v"), "lib")
ui.add_source_files(join(verilog_path, "*.sv"), "lib")
try:
ui.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
def run_sim(self, vhdl_standard):
output_path = join(dirname(abspath(__file__)), 'string_ops_out')
vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl')
ui = VUnit(clean=True,
output_path=output_path,
vhdl_standard=vhdl_standard,
compile_builtins=False)
ui.add_library("lib")
ui.add_builtins("vunit_lib", mock_lang=True)
ui.add_source_files(join(vhdl_path, "string_ops", "test", "*.vhd"), "lib")
try:
ui.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
def run_sim(self, vhdl_standard):
output_path = join(dirname(abspath(__file__)), 'array_out')
src_path = join(dirname(abspath(__file__)), '..', 'vhdl', 'array')
vu = VUnit(clean=True,
output_path=output_path,
vhdl_standard=vhdl_standard)
vu.add_library("lib")
vu.add_array_util("lib")
vu.add_source_files(join(src_path, "test", "*.vhd"), "lib")
try:
vu.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
def run_sim(self, vhdl_standard):
output_path = join(dirname(abspath(__file__)), 'check_out')
vhdl_path = join(dirname(abspath(__file__)), '..', 'vhdl', 'check',
'test')
ui = VUnit(clean=True,
output_path=output_path,
vhdl_standard=vhdl_standard,
compile_builtins=False)
ui.add_builtins('vunit_lib', mock_log=True)
ui.add_library(r'lib')
ui.add_source_files(join(vhdl_path, "test_support.vhd"), 'lib')
if vhdl_standard in ('2002', '2008'):
ui.add_source_files(join(vhdl_path, "test_count.vhd"), 'lib')
ui.add_source_files(join(vhdl_path, "test_types.vhd"), 'lib')
elif vhdl_standard == '93':
ui.add_source_files(join(vhdl_path, "test_count93.vhd"), 'lib')
if vhdl_standard == '2008':
ui.add_source_files(join(vhdl_path, "tb_check_relation.vhd"),
'lib', [CheckPreprocessor()])
else:
ui.add_source_files(
join(vhdl_path, "tb_check_relation93_2002.vhd"), 'lib',
[CheckPreprocessor()])
for file_name in glob(join(vhdl_path, "tb_*.vhd")):
if basename(file_name) == "tb_check_relation.vhd":
continue
ui.add_source_files(file_name, 'lib')
try:
ui.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
