def parse_single_package_body(self, code): """ Helper function to parse a single package body """ design_file = VHDLDesignFile.parse(code) self.assertEqual(len(design_file.package_bodies), 1) return design_file.package_bodies[0]
def parse_single_entity(self, code): """ Helper function to parse a single entity """ design_file = VHDLDesignFile.parse(code) self.assertEqual(len(design_file.entities), 1) return design_file.entities[0]
def parse_single_context(self, code): """ Helper function to parse a single context """ design_file = VHDLDesignFile.parse(code) self.assertEqual(len(design_file.contexts), 1) return design_file.contexts[0]
def test_getting_component_instantiations_from_design_file(self): design_file = VHDLDesignFile.parse(""" entity top is end entity; architecture arch of top is begin labelFoo : component foo generic map(WIDTH => 16) port map(clk => '1', rst => '0', in_vec => record_reg.input_signal, output => some_signal(UPPER_CONSTANT-1 downto LOWER_CONSTANT+1)); label2Foo : foo2 port map(clk => '1', rst => '0', output => "00"); label3Foo : foo3 port map (clk, rst, X"A"); end architecture; """) component_instantiations = design_file.component_instantiations self.assertEqual(len(component_instantiations), 3) self.assertEqual(component_instantiations[0], "foo") self.assertEqual(component_instantiations[1], "foo2") self.assertEqual(component_instantiations[2], "foo3")
def test_parsing_generic_package_instance(self): package = self.parse_single_package("""\ package instance_pkg is new work.generic_pkg; """) self.assertEqual(package.identifier, "instance_pkg") package = self.parse_single_package("""\ package instance_pkg is new work.generic_pkg; """) self.assertEqual(package.identifier, "instance_pkg") package = self.parse_single_package("""\ package instance_pkg is new work.generic_pkg generic map (foo : boolean); """) self.assertEqual(package.identifier, "instance_pkg") # Skip nested packages using the heuristic that the package is # indented from the first column. design_file = VHDLDesignFile.parse("""\ package instance_pkg is new work.generic_pkg """) self.assertEqual(len(design_file.packages), 0)
def test_parsing_references(self): design_file = VHDLDesignFile.parse( """ library name1; use name1.foo.all; library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use name1.bla.all; library lib1,lib2, lib3; use lib1.foo, lib2.bar,lib3.xyz; context name1.is_identifier; entity work1.foo1 entity work1.foo1(a1) for all : bar use entity work2.foo2 for all : bar use entity work2.foo2 (a2) for foo : bar use configuration work.cfg entity foo is -- False configuration bar of ent -- False package new_pkg is new lib.pkg; """ ) self.assertEqual(len(design_file.references), 14) self.assertEqual( sorted(design_file.references, key=repr), sorted( [ VHDLReference("configuration", "work", "cfg", None), VHDLReference("context", "name1", "is_identifier", None), VHDLReference("entity", "work1", "foo1", "a1"), VHDLReference("entity", "work1", "foo1", None), VHDLReference("entity", "work2", "foo2", "a2"), VHDLReference("entity", "work2", "foo2", None), VHDLReference("package", "ieee", "numeric_std", "all"), VHDLReference("package", "ieee", "std_logic_1164", "all"), VHDLReference("package", "lib1", "foo", None), VHDLReference("package", "lib2", "bar", None), VHDLReference("package", "lib3", "xyz", None), VHDLReference("package", "name1", "bla", "all"), VHDLReference("package", "name1", "foo", "all"), VHDLReference("package", "lib", "pkg", None), ], key=repr, ), )
def test_getting_architectures_from_design_file(self): design_file = VHDLDesignFile.parse(""" entity foo is end entity; architecture rtl of foo is begin end architecture; """) self.assertEqual(len(design_file.entities), 1) self.assertEqual(len(design_file.architectures), 1) arch = design_file.architectures self.assertEqual(len(arch), 1) self.assertEqual(arch[0].entity, "foo") self.assertEqual(arch[0].identifier, "rtl")
def test_getting_entities_from_design_file(self): design_file = VHDLDesignFile.parse(""" entity entity1 is end entity; package package1 is end package; entity entity2 is end entity; """) entities = design_file.entities self.assertEqual(len(entities), 2) self.assertEqual(entities[0].identifier, "entity1") self.assertEqual(entities[1].identifier, "entity2")
def test_parsing_references(self): design_file = VHDLDesignFile.parse(""" library name1; use name1.foo.all; library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use name1.bla.all; library lib1,lib2, lib3; use lib1.foo, lib2.bar,lib3.xyz; context name1.is_identifier; entity work1.foo1 entity work1.foo1(a1) for all : bar use entity work2.foo2 for all : bar use entity work2.foo2 (a2) for foo : bar use configuration work.cfg entity foo is -- False configuration bar of ent -- False package new_pkg is new lib.pkg; """) self.assertEqual(len(design_file.references), 14) self.assertEqual( sorted(design_file.references, key=repr), sorted([ VHDLReference('configuration', 'work', 'cfg', None), VHDLReference('context', 'name1', 'is_identifier', None), VHDLReference('entity', 'work1', 'foo1', 'a1'), VHDLReference('entity', 'work1', 'foo1', None), VHDLReference('entity', 'work2', 'foo2', 'a2'), VHDLReference('entity', 'work2', 'foo2', None), VHDLReference('package', 'ieee', 'numeric_std', 'all'), VHDLReference('package', 'ieee', 'std_logic_1164', 'all'), VHDLReference('package', 'lib1', 'foo', None), VHDLReference('package', 'lib2', 'bar', None), VHDLReference('package', 'lib3', 'xyz', None), VHDLReference('package', 'name1', 'bla', 'all'), VHDLReference('package', 'name1', 'foo', 'all'), VHDLReference('package', 'lib', 'pkg', None), ], key=repr))
def test_getting_architectures_from_design_file(self): design_file = VHDLDesignFile.parse( """ entity foo is end entity; architecture rtl of foo is begin end architecture; """ ) self.assertEqual(len(design_file.entities), 1) self.assertEqual(len(design_file.architectures), 1) arch = design_file.architectures self.assertEqual(len(arch), 1) self.assertEqual(arch[0].entity, "foo") self.assertEqual(arch[0].identifier, "rtl")
def test_getting_entities_from_design_file(self): design_file = VHDLDesignFile.parse( """ entity entity1 is end entity; package package1 is end package; entity entity2 is end entity; """ ) entities = design_file.entities self.assertEqual(len(entities), 2) self.assertEqual(entities[0].identifier, "entity1") self.assertEqual(entities[1].identifier, "entity2")
def test_parsing_references(self): design_file = VHDLDesignFile.parse(""" library name1; use name1.foo.all; library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use name1.bla.all; library lib1,lib2, lib3; use lib1.foo, lib2.bar,lib3.xyz; context name1.is_identifier; entity work1.foo1 entity work1.foo1(a1) for all : bar use entity work2.foo2 for all : bar use entity work2.foo2 (a2) for foo : bar use configuration work.cfg entity foo is -- False configuration bar of ent -- False package new_pkg is new lib.pkg; """) self.assertEqual(len(design_file.references), 14) self.assertEqual(sorted(design_file.references, key=repr), sorted([ VHDLReference('configuration', 'work', 'cfg', None), VHDLReference('context', 'name1', 'is_identifier', None), VHDLReference('entity', 'work1', 'foo1', 'a1'), VHDLReference('entity', 'work1', 'foo1', None), VHDLReference('entity', 'work2', 'foo2', 'a2'), VHDLReference('entity', 'work2', 'foo2', None), VHDLReference('package', 'ieee', 'numeric_std', 'all'), VHDLReference('package', 'ieee', 'std_logic_1164', 'all'), VHDLReference('package', 'lib1', 'foo', None), VHDLReference('package', 'lib2', 'bar', None), VHDLReference('package', 'lib3', 'xyz', None), VHDLReference('package', 'name1', 'bla', 'all'), VHDLReference('package', 'name1', 'foo', 'all'), VHDLReference('package', 'lib', 'pkg', None), ], key=repr))
def __init__(self, name, library, file_type='vhdl'): self.name = name self.library = library self.file_type = file_type code = ostools.read_file(self.name) self._md5 = hashlib.md5(code.encode()).hexdigest() if self.file_type == 'vhdl': design_file = VHDLDesignFile.parse(code) self.design_units = self._find_design_units(design_file) self.dependencies = self._find_dependencies(design_file) else: self.design_units = [] self.dependencies = [] for design_unit in self.design_units: if design_unit.is_primary: logger.debug('Adding primary design unit (%s) %s', design_unit.unit_type, design_unit.name) elif design_unit.unit_type == 'package body': logger.debug('Adding secondary design unit (package body) for package %s', design_unit.primary_design_unit) else: logger.debug('Adding secondary design unit (%s) %s', design_unit.unit_type, design_unit.name)
def test_parsing_libraries(self): design_file = VHDLDesignFile.parse(""" library name1; use name1.foo.all; library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use name1.bla.all; library lib1,lib2, lib3; use lib1.foo, lib2.bar,lib3.xyz; context name1.is_identifier; """) self.assertEqual(len(design_file.libraries), 5) self.assertEqual(len(design_file.contexts), 0) self.assertEqual(design_file.libraries, {"ieee" : set([("numeric_std", "all"), ("std_logic_1164", "all")]), "name1" : set([("foo", "all"), ("bla", "all"), ("is_identifier",)]), "lib1" : set([("foo",)]), "lib2" : set([("bar",)]), "lib3" : set([("xyz",)])})
def test_parsing_empty(self): design_file = VHDLDesignFile.parse("") self.assertEqual(design_file.entities, []) self.assertEqual(design_file.packages, []) self.assertEqual(design_file.architectures, [])