def main(args):
nargs = len (args)
if nargs == 1:
outfile = args[0]
else:
sys.stderr.write ('usage: viterbi_out.py output_file\n')
sys.exit (1)
fg = gr.flow_graph()
src = gr.file_source(atsc.sizeof_atsc_soft_data_segment, "/tmp/atsc_pipe_5")
viterbi = atsc.viterbi_decoder()
deinter = atsc.deinterleaver()
rs_dec = atsc.rs_decoder()
derand = atsc.derandomizer()
depad = atsc.depad()
dst = gr.file_sink(gr.sizeof_char,outfile)
fg.connect(src, viterbi, deinter, rs_dec, derand, depad, dst)
fg.run ()
def main(args):
print os.getpid()
nargs = len (args)
if nargs == 1:
outfile = args[0]
else:
sys.stderr.write ('usage: viterbi_out.py output_file\n')
sys.exit (1)
tb = gr.top_block()
src = blocks.file_source(atsc.sizeof_atsc_soft_data_segment, "/tmp/atsc_pipe_5")
viterbi = atsc.viterbi_decoder()
deinter = atsc.deinterleaver()
rs_dec = atsc.rs_decoder()
derand = atsc.derandomizer()
depad = atsc.depad()
dst = blocks.file_sink(gr.sizeof_char,outfile)
tb.connect(src, viterbi, deinter, rs_dec, derand, depad, dst)
tb.run ()
def main(args):
print os.getpid()
nargs = len (args)
if nargs == 1:
outfile = args[0]
else:
sys.stderr.write ('usage: viterbi_out.py output_file\n')
sys.exit (1)
tb = gr.top_block()
src = gr.file_source(atsc.sizeof_atsc_soft_data_segment, "/tmp/atsc_pipe_5")
viterbi = atsc.viterbi_decoder()
deinter = atsc.deinterleaver()
rs_dec = atsc.rs_decoder()
derand = atsc.derandomizer()
depad = atsc.depad()
dst = gr.file_sink(gr.sizeof_char,outfile)
tb.connect(src, viterbi, deinter, rs_dec, derand, depad, dst)
tb.run ()
def graph (args):
print os.getpid()
nargs = len(args)
if nargs == 2:
infile = args[0]
outfile = args[1]
else:
raise ValueError('usage: interp.py input_file output_file.ts\n')
input_rate = 19.2e6
IF_freq = 5.75e6
tb = gr.top_block()
# Read from input file
srcf = blocks.file_source(gr.sizeof_short, infile)
# Convert interleaved shorts (I,Q,I,Q) to complex
is2c = blocks.interleaved_short_to_complex()
# 1/2 as wide because we're designing lp filter
symbol_rate = atsc.ATSC_SYMBOL_RATE/2.
NTAPS = 279
tt = filter.firdes.root_raised_cosine (1.0, input_rate / 3, symbol_rate, .1152, NTAPS)
rrc = filter.fir_filter_ccf(1, tt)
# Interpolate Filter our 6MHz wide signal centered at 0
ilp_coeffs = filter.firdes.low_pass(1, input_rate, 3.2e6, .5e6, filter.firdes.WIN_HAMMING)
ilp = filter.interp_fir_filter_ccf(3, ilp_coeffs)
# Move the center frequency to 5.75MHz ( this wont be needed soon )
duc_coeffs = filter.firdes.low_pass ( 1, 19.2e6, 9e6, 1e6, filter.firdes.WIN_HAMMING )
duc = filter.freq_xlating_fir_filter_ccf ( 1, duc_coeffs, -5.75e6, 19.2e6 )
# fpll input is float
c2f = blocks.complex_to_float()
# Phase locked loop
fpll = atsc.fpll()
# Clean fpll output
lp_coeffs2 = filter.firdes.low_pass (1.0,
input_rate,
5.75e6,
120e3,
filter.firdes.WIN_HAMMING);
lp_filter = filter.fir_filter_fff (1, lp_coeffs2)
# Remove pilot ( at DC now )
iir = filter.single_pole_iir_filter_ff(1e-5)
remove_dc = blocks.sub_ff()
# Bit Timing Loop, Field Sync Checker and Equalizer
btl = atsc.bit_timing_loop()
fsc = atsc.fs_checker()
eq = atsc.equalizer()
fsd = atsc.field_sync_demux()
# Viterbi
viterbi = atsc.viterbi_decoder()
deinter = atsc.deinterleaver()
rs_dec = atsc.rs_decoder()
derand = atsc.derandomizer()
depad = atsc.depad()
# Write to output file
outf = blocks.file_sink(gr.sizeof_char,outfile)
# Connect it all together
tb.connect( srcf, is2c, rrc, ilp, duc, c2f, fpll, lp_filter)
tb.connect( lp_filter, iir )
tb.connect( lp_filter, (remove_dc, 0) )
tb.connect( iir, (remove_dc, 1) )
tb.connect( remove_dc, btl )
tb.connect( (btl, 0), (fsc, 0), (eq, 0), (fsd,0) )
tb.connect( (btl, 1), (fsc, 1), (eq, 1), (fsd,1) )
tb.connect( fsd, viterbi, deinter, rs_dec, derand, depad, outf )
tb.run()
def graph(args):
nargs = len(args)
if nargs == 2:
infile = args[0]
outfile = args[1]
else:
raise ValueError('usage: interp.py input_file output_file\n')
tb = gr.top_block()
# Convert to a from shorts to a stream of complex numbers.
srcf = blocks.file_source(gr.sizeof_short, infile)
s2ss = blocks.stream_to_streams(gr.sizeof_short, 2)
s2f1 = blocks.short_to_float()
s2f2 = blocks.short_to_float()
src0 = blocks.float_to_complex()
tb.connect(srcf, s2ss)
tb.connect((s2ss, 0), s2f1, (src0, 0))
tb.connect((s2ss, 1), s2f2, (src0, 1))
# Low pass filter it and increase sample rate by a factor of 3.
lp_coeffs = filter.firdes.low_pass(3, 19.2e6, 3.2e6, .5e6,
filter.firdes.WIN_HAMMING)
lp = filter.interp_fir_filter_ccf(3, lp_coeffs)
tb.connect(src0, lp)
# Upconvert it.
duc_coeffs = filter.firdes.low_pass(1, 19.2e6, 9e6, 1e6,
filter.firdes.WIN_HAMMING)
duc = filter.freq_xlating_fir_filter_ccf(1, duc_coeffs, 5.75e6, 19.2e6)
# Discard the imaginary component.
c2f = blocks.complex_to_float()
tb.connect(lp, duc, c2f)
# Frequency Phase Lock Loop
input_rate = 19.2e6
IF_freq = 5.75e6
# 1/2 as wide because we're designing lp filter
symbol_rate = atsc.ATSC_SYMBOL_RATE / 2.
NTAPS = 279
tt = filter.firdes.root_raised_cosine(1.0, input_rate, symbol_rate, .115,
NTAPS)
# heterodyne the low pass coefficients up to the specified bandpass
# center frequency. Note that when we do this, the filter bandwidth
# is effectively twice the low pass (2.69 * 2 = 5.38) and hence
# matches the diagram in the ATSC spec.
arg = 2. * math.pi * IF_freq / input_rate
t = []
for i in range(len(tt)):
t += [tt[i] * 2. * math.cos(arg * i)]
rrc = filter.fir_filter_fff(1, t)
fpll = atsc.fpll()
pilot_freq = IF_freq - 3e6 + 0.31e6
lower_edge = 6e6 - 0.31e6
upper_edge = IF_freq - 3e6 + pilot_freq
transition_width = upper_edge - lower_edge
lp_coeffs = filter.firdes.low_pass(1.0, input_rate,
(lower_edge + upper_edge) * 0.5,
transition_width,
filter.firdes.WIN_HAMMING)
lp_filter = filter.fir_filter_fff(1, lp_coeffs)
alpha = 1e-5
iir = filter.single_pole_iir_filter_ff(alpha)
remove_dc = blocks.sub_ff()
tb.connect(c2f, fpll, lp_filter)
tb.connect(lp_filter, iir)
tb.connect(lp_filter, (remove_dc, 0))
tb.connect(iir, (remove_dc, 1))
# Bit Timing Loop, Field Sync Checker and Equalizer
btl = atsc.bit_timing_loop()
fsc = atsc.fs_checker()
eq = atsc.equalizer()
fsd = atsc.field_sync_demux()
tb.connect(remove_dc, btl)
tb.connect((btl, 0), (fsc, 0), (eq, 0), (fsd, 0))
tb.connect((btl, 1), (fsc, 1), (eq, 1), (fsd, 1))
# Viterbi
viterbi = atsc.viterbi_decoder()
deinter = atsc.deinterleaver()
rs_dec = atsc.rs_decoder()
derand = atsc.derandomizer()
depad = atsc.depad()
dst = blocks.file_sink(gr.sizeof_char, outfile)
tb.connect(fsd, viterbi, deinter, rs_dec, derand, depad, dst)
dst2 = blocks.file_sink(gr.sizeof_gr_complex, "atsc_complex.data")
tb.connect(src0, dst2)
tb.run()
def graph (args):
nargs = len(args)
if nargs == 2:
infile = args[0]
outfile = args[1]
else:
raise ValueError('usage: interp.py input_file output_file\n')
tb = gr.top_block ()
# Convert to a from shorts to a stream of complex numbers.
srcf = gr.file_source (gr.sizeof_short,infile)
s2ss = gr.stream_to_streams(gr.sizeof_short,2)
s2f1 = gr.short_to_float()
s2f2 = gr.short_to_float()
src0 = gr.float_to_complex()
tb.connect(srcf, s2ss)
tb.connect((s2ss, 0), s2f1, (src0, 0))
tb.connect((s2ss, 1), s2f2, (src0, 1))
# Low pass filter it and increase sample rate by a factor of 3.
lp_coeffs = gr.firdes.low_pass ( 3, 19.2e6, 3.2e6, .5e6, gr.firdes.WIN_HAMMING )
lp = gr.interp_fir_filter_ccf ( 3, lp_coeffs )
tb.connect(src0, lp)
# Upconvert it.
duc_coeffs = gr.firdes.low_pass ( 1, 19.2e6, 9e6, 1e6, gr.firdes.WIN_HAMMING )
duc = gr.freq_xlating_fir_filter_ccf ( 1, duc_coeffs, 5.75e6, 19.2e6 )
# Discard the imaginary component.
c2f = gr.complex_to_float()
tb.connect(lp, duc, c2f)
# Frequency Phase Lock Loop
input_rate = 19.2e6
IF_freq = 5.75e6
# 1/2 as wide because we're designing lp filter
symbol_rate = atsc.ATSC_SYMBOL_RATE/2.
NTAPS = 279
tt = gr.firdes.root_raised_cosine (1.0, input_rate, symbol_rate, .115, NTAPS)
# heterodyne the low pass coefficients up to the specified bandpass
# center frequency. Note that when we do this, the filter bandwidth
# is effectively twice the low pass (2.69 * 2 = 5.38) and hence
# matches the diagram in the ATSC spec.
arg = 2. * math.pi * IF_freq / input_rate
t=[]
for i in range(len(tt)):
t += [tt[i] * 2. * math.cos(arg * i)]
rrc = gr.fir_filter_fff(1, t)
fpll = atsc.fpll()
pilot_freq = IF_freq - 3e6 + 0.31e6
lower_edge = 6e6 - 0.31e6
upper_edge = IF_freq - 3e6 + pilot_freq
transition_width = upper_edge - lower_edge
lp_coeffs = gr.firdes.low_pass (1.0,
input_rate,
(lower_edge + upper_edge) * 0.5,
transition_width,
gr.firdes.WIN_HAMMING);
lp_filter = gr.fir_filter_fff (1,lp_coeffs)
alpha = 1e-5
iir = gr.single_pole_iir_filter_ff(alpha)
remove_dc = gr.sub_ff()
tb.connect(c2f, fpll, lp_filter)
tb.connect(lp_filter, iir)
tb.connect(lp_filter, (remove_dc,0))
tb.connect(iir, (remove_dc,1))
# Bit Timing Loop, Field Sync Checker and Equalizer
btl = atsc.bit_timing_loop()
fsc = atsc.fs_checker()
eq = atsc.equalizer()
fsd = atsc.field_sync_demux()
tb.connect(remove_dc, btl)
tb.connect((btl, 0),(fsc, 0),(eq, 0),(fsd, 0))
tb.connect((btl, 1),(fsc, 1),(eq, 1),(fsd, 1))
# Viterbi
viterbi = atsc.viterbi_decoder()
deinter = atsc.deinterleaver()
rs_dec = atsc.rs_decoder()
derand = atsc.derandomizer()
depad = atsc.depad()
dst = gr.file_sink(gr.sizeof_char, outfile)
tb.connect(fsd, viterbi, deinter, rs_dec, derand, depad, dst)
dst2 = gr.file_sink(gr.sizeof_gr_complex, "atsc_complex.data")
tb.connect(src0, dst2)
tb.run ()
def graph(args):
print os.getpid()
nargs = len(args)
if nargs == 2:
infile = args[0]
outfile = args[1]
else:
raise ValueError('usage: interp.py input_file output_file.ts\n')
input_rate = 19.2e6
IF_freq = 5.75e6
tb = gr.top_block()
# Read from input file
srcf = blocks.file_source(gr.sizeof_short, infile)
# Convert interleaved shorts (I,Q,I,Q) to complex
is2c = blocks.interleaved_short_to_complex()
# 1/2 as wide because we're designing lp filter
symbol_rate = atsc.ATSC_SYMBOL_RATE / 2.
NTAPS = 279
tt = filter.firdes.root_raised_cosine(1.0, input_rate / 3, symbol_rate,
.1152, NTAPS)
rrc = filter.fir_filter_ccf(1, tt)
# Interpolate Filter our 6MHz wide signal centered at 0
ilp_coeffs = filter.firdes.low_pass(1, input_rate, 3.2e6, .5e6,
filter.firdes.WIN_HAMMING)
ilp = filter.interp_fir_filter_ccf(3, ilp_coeffs)
# Move the center frequency to 5.75MHz ( this won't be needed soon )
duc_coeffs = filter.firdes.low_pass(1, 19.2e6, 9e6, 1e6,
filter.firdes.WIN_HAMMING)
duc = filter.freq_xlating_fir_filter_ccf(1, duc_coeffs, -5.75e6, 19.2e6)
# fpll input is float
c2f = blocks.complex_to_float()
# Phase locked loop
fpll = atsc.fpll()
# Clean fpll output
lp_coeffs2 = filter.firdes.low_pass(1.0, input_rate, 5.75e6, 120e3,
filter.firdes.WIN_HAMMING)
lp_filter = filter.fir_filter_fff(1, lp_coeffs2)
# Remove pilot ( at DC now )
iir = filter.single_pole_iir_filter_ff(1e-5)
remove_dc = blocks.sub_ff()
# Bit Timing Loop, Field Sync Checker and Equalizer
btl = atsc.bit_timing_loop()
fsc = atsc.fs_checker()
eq = atsc.equalizer()
fsd = atsc.field_sync_demux()
# Viterbi
viterbi = atsc.viterbi_decoder()
deinter = atsc.deinterleaver()
rs_dec = atsc.rs_decoder()
derand = atsc.derandomizer()
depad = atsc.depad()
# Write to output file
outf = blocks.file_sink(gr.sizeof_char, outfile)
# Connect it all together
tb.connect(srcf, is2c, rrc, ilp, duc, c2f, fpll, lp_filter)
tb.connect(lp_filter, iir)
tb.connect(lp_filter, (remove_dc, 0))
tb.connect(iir, (remove_dc, 1))
tb.connect(remove_dc, btl)
tb.connect((btl, 0), (fsc, 0), (eq, 0), (fsd, 0))
tb.connect((btl, 1), (fsc, 1), (eq, 1), (fsd, 1))
tb.connect(fsd, viterbi, deinter, rs_dec, derand, depad, outf)
tb.run()