def init(self, signals): self.out_file = open(self.filename, "w") # generate codes for signal in signals: try: code = self.codes[signal] except KeyError: code = next(self.codegen) self.codes[signal] = code # write vcd header header = "" ns = build_namespace(self.codes.keys()) for signal, code in self.codes.items(): name = ns.get_name(signal) header += "$var wire {len} {code} {name} $end\n".format(name=name, code=code, len=len(signal)) header += "$dumpvars\n" for signal in self.codes.keys(): header += self._write_value(signal, signal.reset.value) header += "$end\n" self.out_file.write(header) if self.initialized: self.buffer_file.seek(0) shutil.copyfileobj(self.buffer_file, self.out_file) self.buffer_file.seek(0, 2) else: # init time self._write("#0\n") self.initialized = True
def convert(f, ios=None, name="top", special_overrides=dict(), create_clock_domains=True, display_run=False, reg_initialization=True, dummy_signal=True, blocking_assign=False, regular_comb=True): r = ConvOutput() if not isinstance(f, _Fragment): f = f.get_fragment() if ios is None: ios = set() for cd_name in sorted(list_clock_domains(f)): try: f.clock_domains[cd_name] except KeyError: if create_clock_domains: cd = ClockDomain(cd_name) f.clock_domains.append(cd) ios |= {cd.clk, cd.rst} else: raise KeyError("Unresolved clock domain: '"+cd_name+"'") f = lower_complex_slices(f) insert_resets(f) f = lower_basics(f) fs, lowered_specials = lower_specials(special_overrides, f.specials) f += lower_basics(fs) for io in sorted(ios, key=lambda x: x.duid): if io.name_override is None: io_name = io.backtrace[-1][0] if io_name: io.name_override = io_name ns = build_namespace(list_signals(f) \ | list_special_ios(f, True, True, True) \ | ios, _reserved_keywords) ns.clock_domains = f.clock_domains r.ns = ns src = "/* Machine-generated using LiteX gen */\n" src += _printheader(f, ios, name, ns, reg_initialization=reg_initialization) src += _printcomb(f, ns, display_run=display_run, dummy_signal=dummy_signal, blocking_assign=blocking_assign) src += _printsync(f, ns) src += _printspecials(special_overrides, f.specials - lowered_specials, ns, r.add_data_file) src += "endmodule\n" r.set_main_source(src) return r
def init(self, signals): # generate codes for signal in signals: try: code = self.codes[signal] except KeyError: code = next(self.codegen) self.codes[signal] = code # write vcd header out = self.out_file ns = build_namespace(self.codes.keys()) for signal, code in self.codes.items(): name = ns.get_name(signal) out.write("$var wire {len} {code} {name} $end\n".format( name=name, code=code, len=len(signal))) out.write("$dumpvars\n") for signal in self.codes.keys(): self._write_value(out, signal, signal.reset.value) out.write("$end\n") out.write("#0\n")
def convert(f, ios=set(), name="top", platform=None, special_overrides = dict(), attr_translate = DummyAttrTranslate(), regular_comb = True): # Create ConvOutput. r = ConvOutput() # Convert to FHDL's fragments is not already done. if not isinstance(f, _Fragment): f = f.get_fragment() # Verify/Create Clock Domains. for cd_name in sorted(list_clock_domains(f)): # Try to get Clock Domain. try: f.clock_domains[cd_name] # If not found, raise Error. except: msg = f"""Unresolved clock domain {cd_name}, availables:\n""" for f in f.clock_domains: msg += f"- {f.name}\n" raise Exception(msg) # Lower complex slices. f = lower_complex_slices(f) # Insert resets. insert_resets(f) # Lower basics. f = lower_basics(f) # Lower specials. if platform is not None: for s in f.specials: s.platform = platform f, lowered_specials = lower_specials(special_overrides, f) # Lower basics (for basics included in specials). f = lower_basics(f) # IOs collection (when not specified). if len(ios) == 0: assert platform is not None ios = platform.constraint_manager.get_io_signals() # IOs backtrace/naming. for io in sorted(ios, key=lambda x: x.duid): if io.name_override is None: io_name = io.backtrace[-1][0] if io_name: io.name_override = io_name # Build NameSpace. # ---------------- ns = build_namespace( signals = ( list_signals(f) | list_special_ios(f, ins=True, outs=True, inouts=True) | ios), reserved_keywords = _ieee_1800_2017_verilog_reserved_keywords ) ns.clock_domains = f.clock_domains # Build Verilog. # -------------- verilog = "" verilog += _print_banner( filename = name, device = getattr(platform, "device", "Unknown") ) # Module Definition. verilog += _print_separator("Module") verilog += _print_module(f, ios, name, ns, attr_translate) # Module Signals. verilog += _print_separator("Signals") verilog += _print_signals(f, ios, name, ns, attr_translate) # Combinatorial Logic. verilog += _print_separator("Combinatorial Logic") if regular_comb: verilog += _print_combinatorial_logic_synth(f, ns) else: verilog += _print_combinatorial_logic_sim(f, ns) # Synchronous Logic. verilog += _print_separator("Synchronous Logic") verilog += _print_synchronous_logic(f, ns) # Specials verilog += _print_separator("Specialized Logic") verilog += _print_specials( name = name, overrides =special_overrides, specials = f.specials - lowered_specials, namespace = ns, add_data_file = r.add_data_file, attr_translate = attr_translate ) # Module End. verilog += "endmodule\n" verilog += _print_trailer() r.set_main_source(verilog) r.ns = ns return r
def convert(f, ios=None, name="top", special_overrides=dict(), attr_translate=DummyAttrTranslate(), create_clock_domains=True, display_run=False, reg_initialization=True, dummy_signal=True, blocking_assign=False, regular_comb=True): r = ConvOutput() if not isinstance(f, _Fragment): f = f.get_fragment() if ios is None: ios = set() for cd_name in sorted(list_clock_domains(f)): try: f.clock_domains[cd_name] except KeyError: if create_clock_domains: cd = ClockDomain(cd_name) f.clock_domains.append(cd) ios |= {cd.clk, cd.rst} else: print("available clock domains:") for f in f.clock_domains: print(f.name) raise KeyError("Unresolved clock domain: '"+cd_name+"'") f = lower_complex_slices(f) insert_resets(f) f = lower_basics(f) fs, lowered_specials = lower_specials(special_overrides, f.specials) f += lower_basics(fs) for io in sorted(ios, key=lambda x: x.duid): if io.name_override is None: io_name = io.backtrace[-1][0] if io_name: io.name_override = io_name ns = build_namespace(list_signals(f) \ | list_special_ios(f, True, True, True) \ | ios, _reserved_keywords) ns.clock_domains = f.clock_domains r.ns = ns src = "/* Machine-generated using LiteX gen */\n" src += _printheader(f, ios, name, ns, attr_translate, reg_initialization=reg_initialization) if regular_comb: src += _printcomb_regular(f, ns, blocking_assign=blocking_assign) else: src += _printcomb_simulation(f, ns, display_run=display_run, dummy_signal=dummy_signal, blocking_assign=blocking_assign) src += _printsync(f, ns) src += _printspecials(special_overrides, f.specials - lowered_specials, ns, r.add_data_file, attr_translate) src += "endmodule\n" r.set_main_source(src) return r