def _give_bits(e, extend=False): if isinstance(e, Value): l,s = value_bits_sign(e) for n in range(l): yield e[n] if extend: while True: if s: yield e[l-1] else: yield 0 elif isinstance(e, bool): if e: yield 1 else: yield 0 if extend: while True: yield 0 else: return elif isinstance(e, int): n = e s = 1 if e < 0 else 0 while n != 0: yield n & 1 n = n >> 1 if extend: while True: yield s else: return else: raise ValueError("I don't know how to slice {}.".format(e))
def __init__(self, a, b, s, sub=False): bits, signed = value_bits_sign(s) cin = 0 op1 = _give_bits(a, extend=True) op2 = _give_bits(~b, extend=True) if sub else _give_bits(b, extend=True) for bop1, bop2, res in zip(op1, op2, _give_bits(s, extend=False)): carry = Signal() self.submodules += Fulladder(bop1, bop2, res, cin, carry) cin = carry
def __init__(self, a, b, s, sub=False): bits, signed = value_bits_sign(s) cin = 0 op1 = _give_bits(a, extend=True) op2 = _give_bits(~b, extend=True) if sub else _give_bits(b, extend=True) for bop1, bop2, res in zip(op1, op2, _give_bits(s, extend=False)): cout = Signal() x = bop1 ^ bop2 self.specials += Instance("XORCY", i_CI=cin, i_LI=x, o_O=res) self.specials += Instance("MUXCY", i_CI=cin, i_DI=bop2, i_S=x, o_O=cout) cin = cout
def visit_ArrayProxy(self, node): array_muxed = Signal(value_bits_sign(node), variable=True) if self.target_context: k = self.visit(node.key) cases = {} for n, choice in enumerate(node.choices): cases[n] = [self.visit_Assign(_Assign(choice, array_muxed))] self.extra_stmts.append(Case(k, cases).makedefault()) else: cases = dict((n, _Assign(array_muxed, self.visit(choice))) for n, choice in enumerate(node.choices)) self.comb.append(Case(self.visit(node.key), cases).makedefault()) return array_muxed
def extract_special_expr(f): for sp in f.specials: for obj, attr, x in sp.iter_expressions(): expr = getattr(obj, attr) if not isinstance(expr, Signal): rell = list_signals(expr) if rell: rel = min(rell, key=lambda x: x.huid) else: rel = None s_expr = Signal(value_bits_sign(expr), related=rel) f.comb.append(s_expr.eq(expr)) setattr(obj, attr, s_expr)
def __init__(self, i, o, odomain, n): self.i = i self.o = o self.odomain = odomain w, signed = value_bits_sign(self.i) self.regs = [Signal((w, signed)) for i in range(n)] ### src = self.i for reg in self.regs: sd = getattr(self.sync, self.odomain) sd += reg.eq(src) src = reg self.comb += self.o.eq(src) self.specials += [NoRetiming(reg) for reg in self.regs]
def emit_verilog(tristate, ns): def pe(e): return verilog_printexpr(ns, e)[0] w, s = value_bits_sign(tristate.target) r = ( "assign " + pe(tristate.target) + " = " + pe(tristate.oe) + " ? " + pe(tristate.o) + " : " + str(w) + "'bz;\n" ) if tristate.i is not None: r += "assign " + pe(tristate.i) + " = " + pe(tristate.target) + ";\n" r += "\n" return r