def test_pymtl_list_components(): a = CaseBits32InOutx5CompOnly.DUT() a.elaborate() assert rt.is_rtlir_convertible(a.b) assert rt.get_rtlir( a.b ) == \ rt.Array([5], rt.Component( a.b[0], { 'clk':rt.Port('input', rdt.Vector(1)), 'reset':rt.Port('input', rdt.Vector(1)), 'in_':rt.Port('input', rdt.Vector(32)), 'out':rt.Port('output', rdt.Vector(32)), }))
def test_pymtl_list_components(): class B(dsl.Component): def construct(s): s.in_ = dsl.InPort(Bits32) s.out = dsl.OutPort(Bits32) class A(dsl.Component): def construct(s): s.b = [B() for _ in range(5)] a = A() a.elaborate() assert rt.is_rtlir_convertible(a.b) assert rt.Array([5], rt.Component( a.b[0], {'in_':rt.Port('input', rdt.Vector(32)), 'out':rt.Port('output', rdt.Vector(32))})) == \ rt.get_rtlir( a.b )