def run_sim(self, vhdl_standard):
output_path = join(dirname(abspath(__file__)), 'array_out')
src_path = join(dirname(abspath(__file__)), '..', 'vhdl', 'array')
vu = VUnit(clean=True,
output_path=output_path,
vhdl_standard=vhdl_standard)
vu.add_library("lib")
vu.add_array_util("lib")
vu.add_source_files(join(src_path, "test", "*.vhd"), "lib")
try:
vu.main()
except SystemExit as e:
self.assertEqual(e.code, 0)
