An FPGA placement framework implemented in Java, including benchmarks

• Simulated Annealing Placement
• Analytical Solver Iterative Placement
• Steepest Gradient Descent Iterative Placement

Some parts of this toolflow require external packages, you can find these in the file "requirements".

To calculate point to point delays, vpr is used (see option --vpr_command). When compiling vpr, the macro PRINT_ARRAYS has to be defined in "place/timing_place_lookup.c".

Architecture files are currently json-formatted and based on the vpr xml-files.

The command line options can be found by calling interfaces.CLI with the option "--help". The most simple invocation of the toolflow is:

java -cp bin:lib/json-simple-1.1.1.jar interfaces.CLI
benchmarks/k6_frac_N10_mem32K_40nm.xml benchmarks/or1200.blif --placer wld_ap

The FPGA Placement Framework is licensed by Ghent University. The license is included in all licensed code and in the repository, it is also printed below.

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The FPGA Placement Framework is released by Ghent University, ELIS department, Hardware and Embedded Systems (HES) group (http://hes.elis.ugent.be).

If you encounter bugs, want to use the FPGA Placement Framework but need support or want to tell us about your results, please contact us. We can be reached at Elias.Vansteenkiste@gmail.com

If you use the FPGA Placement Framework in your work, please reference in your publications the following paper:

You may also refer to one of our others papers if you think it is more related.

Active Contributors

• Seppe Lenders - Seppe.Lenders@gmail.com
• Elias Vansteenkiste - Elias.Vansteenkiste@gmail.com

Past Contributors

• Arno Messiaen - Arno.Messiaen@gmail.com

The FPGA Placement Framework is a work in progress, input is welcome.