def get_sch_master(module_db: ModuleDB,
sch_design_params: Dict[str, Any]) -> Module:
lib_name = sch_design_params['lib_name']
cell_name = sch_design_params['cell_name']
params = sch_design_params['params']
gen_cls = cast(Type[Module],
module_db.get_schematic_class(lib_name, cell_name))
ans = module_db.new_master(gen_cls, params=params)
return ans
def generate(prj,
temp_lib,
impl_lib,
cell_name,
lay_params,
sch_params,
mdl_params,
grid_opts,
mdl_dir,
mdl_opts=None,
impl_cell_name=None):
"""
generate layout, schematic and model.
"""
# temp_db = make_tdb(prj, impl_loib, grid_opts)
#
# print('designing module')
# # layout
# print(lay_params)
# template = temp_db.new_template(params=lay_params, temp_cls=NAND, debug=True)
# if impl_cell_name is None:
# temp_db.instantiate_layout(prj, template, cell_name, debug=True)
# else:
# temp_db.instantiate_layout(prj, template, impl_cell_name, debug=True)
# generate schematic
if sch_params is None:
sch_params = {}
# sch_params.update(template.sch_params)
print(sch_params)
sch_db = ModuleDB(prj.tech_info, impl_lib, prj=prj)
gen_cls = sch_db.get_schematic_class(temp_lib, cell_name)
dsn = sch_db.new_master(gen_cls, params=sch_params)
if impl_cell_name is None:
sch_db.instantiate_master(DesignOutput.SCHEMATIC, dsn)
else:
sch_db.instantiate_master(DesignOutput.SCHEMATIC,
dsn,
top_cell_name=impl_cell_name)
# generate model
file_name = f"{mdl_dir}/{cell_name}.sv"
top_cell_name = cell_name if impl_cell_name is None else impl_cell_name
if mdl_opts is None:
mdl_opts = {}
sch_db.instantiate_model(dsn,
mdl_params,
top_cell_name=top_cell_name,
fname=file_name,
**mdl_opts)
def __init__(self, bprj: BagProject, spec_file: str = '',
spec_dict: Optional[Mapping[str, Any]] = None,
sch_db: Optional[ModuleDB] = None, lay_db: Optional[TemplateDB] = None,
extract: bool = False) -> None:
if spec_dict:
params = spec_dict
else:
params = read_yaml(spec_file)
self.params = cast(Dict[str, Any], params)
self._root_dir = Path(self.params['root_dir']).resolve()
self._prj = bprj
if sch_db is None:
self._sch_db = ModuleDB(bprj.tech_info, self.params['impl_lib'], prj=bprj)
else:
self._sch_db = sch_db
if lay_db is None:
self._lay_db = TemplateDB(bprj.grid, self.params['impl_lib'], prj=bprj)
else:
self._lay_db = lay_db
self.extract = extract
self.data = {} # a dictionary to access package resources
self.designed_params = {} # the parameters after design has been done
self.designed_performance = {} # the performance metrics that designed params satisfy
def run_main(prj: BagProject, gen_sch: bool = True, gen_cdl: bool = True, run_lvs: bool = True) \
-> None:
lib_name = 'AAA_XBASE_TEST'
fname = '00_mom_cap.yaml'
impl_cell = 'MOMCap_core'
fname_cdl = 'pvs_run/lvs_run_dir/' + lib_name + '/' + impl_cell + '/schematic.net'
params = read_yaml(Path('specs_test', 'xbase', fname))
db = TemplateDB(prj.grid, lib_name, prj=prj)
print('creating new template')
master = db.new_template(MOMCapCore, params)
print('creating batch layout')
# db.batch_layout([(master, '')], DesignOutput.LAYOUT)
db.batch_layout([(master, impl_cell)], DesignOutput.LAYOUT)
print('done')
if gen_sch or gen_cdl:
sch_db = ModuleDB(prj.tech_info, lib_name, prj=prj)
sch_master = sch_db.new_master(xbase__momcap_core, master.sch_params)
cv_info_list = []
print('creating schematic')
sch_db.batch_schematic([(sch_master, impl_cell)],
cv_info_out=cv_info_list)
print('schematic creation done')
if gen_cdl:
print('creating CDL netlist')
sch_db.batch_schematic([(sch_master, impl_cell)],
output=DesignOutput.CDL,
fname=fname_cdl,
cv_info_list=cv_info_list)
print('netlist creation done')
if run_lvs:
print('Running LVS ...')
lvs_passed, lvs_log = prj.run_lvs(lib_name,
impl_cell,
netlist=fname_cdl)
print('LVS log file:' + lvs_log)
if lvs_passed:
print('LVS passed!')
else:
print('LVS failed :(')
def generate_wrapper(sch_db: ModuleDB, wrapper_params: Dict[str, Any],
cv_info_list: List, dut_netlist: str,
gen_sch: bool) -> None:
wrapper_lib = wrapper_params.pop('wrapper_lib')
wrapper_cell = wrapper_params.pop('wrapper_cell')
wrapper_impl_cell = wrapper_params.pop('impl_cell')
wrapper_netlist_path = Path(wrapper_params.pop('netlist_file'))
wrapper_netlist_path.parent.mkdir(parents=True, exist_ok=True)
wrapper_cls = sch_db.get_schematic_class(wrapper_lib, wrapper_cell)
wrapper_master = sch_db.new_master(wrapper_cls,
params=wrapper_params['params'])
wrapper_list = [(wrapper_master, wrapper_impl_cell)]
sch_db.batch_schematic(wrapper_list,
output=DesignOutput.SPECTRE,
fname=str(wrapper_netlist_path),
cv_info_list=cv_info_list,
cv_netlist=dut_netlist)
print(f'wrapper_netlist: {str(wrapper_netlist_path)}')
if gen_sch:
sch_db.batch_schematic(wrapper_list, output=DesignOutput.SCHEMATIC)
def get_schematic_class(cls) -> Optional[Type[Module]]:
# noinspection PyTypeChecker
return ModuleDB.get_schematic_class('aib_ams', 'aib_frontend')
def get_schematic_class(cls) -> Optional[Type[Module]]:
# noinspection PyTypeChecker
return ModuleDB.get_schematic_class('bag3_digital', 'flop_scan_rstlb')
def get_schematic_class(cls) -> Optional[Type[Module]]:
# noinspection PyTypeChecker
return ModuleDB.get_schematic_class('aib_ams',
'aib_driver_output_driver')
def get_schematic_class(cls) -> Optional[Type[Module]]:
# noinspection PyTypeChecker
return ModuleDB.get_schematic_class('bag3_digital',
'lvshift_core_w_drivers')
def get_schematic_class(cls) -> Optional[Type[Module]]:
# noinspection PyTypeChecker
return ModuleDB.get_schematic_class('tutorial_ams', 'nor')
def test_design(
tmpdir,
module_db: ModuleDB,
sch_design_params: Dict[str, Any],
output_type: DesignOutput,
options: Dict[str, Any],
gen_output: bool,
) -> None:
"""Test design() method of each schematic generator."""
if sch_design_params is None:
# No schematic tests
return
impl_cell = sch_design_params['top_cell_name']
extension = get_extension(output_type)
if is_model_type(output_type):
model_params = sch_design_params.get('model_params', None)
if model_params is None:
pytest.skip('Cannot find model parameters.')
else:
model_params = None
out_code = int(options.get(
'shell', False)) + 2 * (1 - int(options.get('top_subckt', True)))
if output_type is DesignOutput.YAML:
base = 'out'
else:
base = f'out_{out_code}'
expect_fname = sch_design_params.get('{}_{}'.format(base, extension), '')
if not expect_fname and not gen_output:
pytest.skip('Cannot find expected output file.')
dsn = get_sch_master(module_db, sch_design_params)
out_base_name = '{}.{}'.format(base, extension)
path = tmpdir.join(out_base_name)
if is_model_type(output_type):
module_db.batch_model([(dsn, impl_cell, model_params)],
output=output_type,
fname=str(path),
**options)
else:
module_db.instantiate_master(output_type,
dsn,
top_cell_name=impl_cell,
fname=str(path),
**options)
assert path.check(file=1)
with path.open('r') as f:
actual = f.read()
if gen_output:
dir_name = pathlib.Path(
'pytest_output') / sch_design_params['test_output_dir']
out_fname = dir_name / out_base_name
dir_name.mkdir(parents=True, exist_ok=True)
with out_fname.open('w') as f:
f.write(actual)
expect = actual
else:
with open(expect_fname, 'r') as f:
expect = f.read()
if output_type is DesignOutput.YAML:
actual_dict = read_yaml_str(actual)
expect_dict = read_yaml_str(expect)
assert actual_dict == expect_dict
else:
check_netlist(output_type, actual, expect)
def module_db(tech_info: TechInfo) -> ModuleDB:
return ModuleDB(tech_info, 'PYTEST')