def __init__(self, observation_dim, motor_obs_dim, n_action, rl, train,
modelp):
super(CognitiveArchitecture, self).__init__()
self.make_in_port('observation', observation_dim)
self.make_in_port('reward', 1)
self.make_in_port('done', 1)
self.make_out_port('action', 1)
self.make_in_port('token_in', 1)
self.make_out_port('token_out', 1)
if modelp:
self.visual = ModeledVisualComponent(observation_dim,
motor_obs_dim)
else:
self.visual = PipeVisualComponent()
self.motor = MotorComponent(observation_dim, n_action, rl, train)
self.add_component('visual', self.visual)
self.add_component('motor', self.motor)
self.visual.alias_in_port(self, 'observation', 'in')
self.visual.alias_in_port(self, 'token_in', 'token_in')
self.motor.alias_in_port(self, 'reward', 'reward')
self.motor.alias_in_port(self, 'done', 'done')
self.motor.alias_out_port(self, 'action', 'action')
self.motor.alias_out_port(self, 'token_out', 'token_out')
brica1.connect((self.visual, 'out'), (self.motor, 'observation'))
brica1.connect((self.visual, 'token_out'), (self.motor, 'token_in'))
def test_component(self):
s = brica1.VirtualTimeSyncScheduler(1.0)
agent = brica1.Agent(s)
zero = numpy.zeros(3, dtype=numpy.short)
v = numpy.array([1, 2, 3], dtype=numpy.short)
CompA = brica1.ConstantComponent()
CompB = brica1.PipeComponent()
CompC = brica1.NullComponent()
ModA = brica1.Module()
ModA.add_component("CompA", CompA)
ModA.add_component("CompB", CompB)
ModA.add_component("CompC", CompC)
CompA.set_state("out", v)
CompA.make_out_port("out", 3)
CompB.make_in_port("in", 3)
brica1.connect((CompA, "out"), (CompB, "in"))
CompB.make_out_port("out", 3)
CompB.set_map("in", "out")
CompC.make_in_port("in", 3)
brica1.connect((CompB, "out"), (CompC, "in"))
agent.add_submodule("ModA", ModA)
self.assertTrue((CompA.get_state("out") == v).all())
self.assertIsNot(CompA.get_state("out"), v)
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == v ).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
def _(bm):
s = brica1.VirtualTimeSyncScheduler(1.0)
agent = brica1.Agent(s)
compA = brica1.ConstantComponent()
compB = brica1.NullComponent()
mod = brica1.Module();
mod.add_component('compA', compA)
mod.add_component('compB', compB)
compA.make_out_port('out', 256*256*3)
compB.make_in_port('in', 256*256*3)
brica1.connect((compA, 'out'), (compB, 'in'))
agent.add_submodule('mod', mod)
for _ in bm:
agent.step()
def _(bm):
s = brica1.VirtualTimeSyncScheduler(1.0)
agent = brica1.Agent(s)
compA = brica1.ConstantComponent()
compB = brica1.NullComponent()
mod = brica1.Module()
mod.add_component("compA", compA)
mod.add_component("compB", compB)
compA.make_out_port("out", 256 * 256 * 3)
compB.make_in_port("in", 256 * 256 * 3)
brica1.connect((compA, "out"), (compB, "in"))
agent.add_submodule("mod", mod)
for _ in bm:
agent.step()
def relayer():
Comp = brica1.PipeComponent()
Comp.make_in_port("in", 3)
Comp.make_out_port("out", 3)
Comp.set_map("in", "out")
Mod = brica1.Module()
Mod.make_in_port("in", 3)
Mod.make_out_port("out", 3)
Mod.add_component("Comp", Comp)
Scheduler = brica1.RealTimeSyncScheduler()
Agent = brica1.Agent(Scheduler)
Agent.make_in_port("in", 3)
Agent.make_out_port("out", 3)
Agent.add_submodule("Mod", Mod)
brica1.alias_in_port((Agent, "in"), (Mod, "in"))
brica1.alias_out_port((Agent, "out"), (Mod, "out"))
brica1.alias_in_port((Mod, "in"), (Comp, "in"))
brica1.alias_out_port((Mod, "out"), (Comp, "out"))
def converter(msg):
return np.array(list(msg.data), dtype=np.int16)
Adapter = brica1.ros.ROSAdapter("relayer")
Adapter.setup_subscriber("chatter0", Int16MultiArray, "out", 3, converter)
Adapter.setup_publisher("chatter1", "in", 3)
brica1.connect((Adapter, "out"), (Agent, "in"))
brica1.connect((Agent, "out"), (Adapter, "in"))
while not rospy.is_shutdown():
Agent.step()
print "Agent in port: {}".format(Agent.get_in_port("in").buffer)
print "Agent out port: {}".format(Agent.get_out_port("out").buffer)
def relayer():
Comp = brica1.PipeComponent()
Comp.make_in_port("in", 3)
Comp.make_out_port("out", 3)
Comp.set_map("in", "out")
Mod = brica1.Module()
Mod.make_in_port("in", 3)
Mod.make_out_port("out", 3)
Mod.add_component("Comp", Comp)
Scheduler = brica1.RealTimeSyncScheduler()
Agent = brica1.Agent(Scheduler)
Agent.make_in_port("in", 3)
Agent.make_out_port("out", 3)
Agent.add_submodule("Mod", Mod)
brica1.alias_in_port((Agent, "in"), (Mod, "in"))
brica1.alias_out_port((Agent, "out"), (Mod, "out"))
brica1.alias_in_port((Mod, "in"), (Comp, "in"))
brica1.alias_out_port((Mod, "out"), (Comp, "out"))
def converter(msg):
return np.array(list(msg.data), dtype=np.int16)
Adapter = brica1.ros.ROSAdapter("relayer")
Adapter.setup_subscriber("chatter0", Int16MultiArray, "out", 3, converter)
Adapter.setup_publisher("chatter1", "in", 3)
brica1.connect((Adapter, "out"), (Agent, "in"))
brica1.connect((Agent, "out"), (Adapter, "in"))
while not rospy.is_shutdown():
Agent.step()
print "Agent in port: {}".format(Agent.get_in_port("in").buffer)
print "Agent out port: {}".format(Agent.get_out_port("out").buffer)
def test_nested(self):
s = brica1.VirtualTimeSyncScheduler(1.0)
ca = brica1.Agent(s)
zero = numpy.zeros(3, dtype=numpy.short)
v = numpy.array([1, 2, 3], dtype=numpy.short)
CompA = brica1.ConstantComponent()
CompB = brica1.PipeComponent()
CompC = brica1.NullComponent()
ModA = brica1.Module()
ModB = brica1.Module()
ModC = brica1.Module()
SupA = brica1.Module()
SupB = brica1.Module()
SupC = brica1.Module()
Top = brica1.Module()
CompA.set_state("out", v)
CompA.make_out_port("out", 3)
CompB.make_in_port("in", 3)
CompB.make_out_port("out", 3)
CompB.set_map("in", "out")
CompC.make_in_port("in", 3)
ModA.make_out_port("out", 3)
ModB.make_in_port("in", 3)
ModB.make_out_port("out", 3)
ModC.make_in_port("in", 3)
SupA.make_out_port("out", 3)
SupB.make_in_port("in", 3)
SupB.make_out_port("out", 3)
SupC.make_in_port("in", 3)
SupA.add_submodule("ModA", ModA)
SupB.add_submodule("ModB", ModB)
SupC.add_submodule("ModC", ModC)
ModA.add_component("CompA", CompA)
ModB.add_component("CompB", CompB)
ModC.add_component("CompC", CompC)
# Out ports must be aliased inside-out
brica1.alias_out_port((ModA, "out"), (CompA, "out"))
brica1.alias_out_port((SupA, "out"), (ModA, "out"))
# In ports must be aliased outside-in
brica1.alias_in_port((SupB, "in"), (ModB, "in"))
brica1.alias_in_port((ModB, "in"), (CompB, "in"))
# Out ports must be aliased inside-out
brica1.alias_out_port((ModB, "out"), (CompB, "out"))
brica1.alias_out_port((SupB, "out"), (ModB, "out"))
# In ports must be aliased outside-in
brica1.alias_in_port((SupC, "in"), (ModC, "in"))
brica1.alias_in_port((ModC, "in"), (CompC, "in"))
brica1.connect((SupA, "out"), (SupB, "in"))
brica1.connect((SupB, "out"), (SupC, "in"))
Top.add_submodule("SupA", SupA)
Top.add_submodule("SupB", SupB)
Top.add_submodule("SupC", SupC)
ca.add_submodule("Top", Top)
self.assertTrue((CompA.get_state("out") == v).all())
self.assertIsNot(CompA.get_state("out"), v)
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == zero).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == v ).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == v ).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == v ).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
self.assertTrue((ModA.get_out_port("out").buffer == v).all())
self.assertTrue((ModB.get_in_port("in").buffer == v).all())
self.assertTrue((ModB.get_out_port("out").buffer == v).all())
self.assertTrue((ModC.get_in_port("in").buffer == v).all())
self.assertTrue((SupA.get_out_port("out").buffer == v).all())
self.assertTrue((SupB.get_in_port("in").buffer == v).all())
self.assertTrue((SupB.get_out_port("out").buffer == v).all())
self.assertTrue((SupC.get_in_port("in").buffer == v).all())
num.offset = 0.0
cnn.offset = 1.0
rnn.offset = 2.0
num.interval = 3.0
cnn.interval = 3.0
rnn.interval = 3.0
mod = brica1.Module()
mod.add_component("num", num)
mod.add_component("cnn", cnn)
mod.add_component("rnn", rnn)
num.make_out_port("out", 1)
cnn.make_in_port("in", 1)
cnn.make_out_port("out", 1)
rnn.make_in_port("in", 1)
brica1.connect((num, "out"), (cnn, "in"))
brica1.connect((cnn, "out"), (rnn, "in"))
s = brica1.VirtualTimeScheduler()
ca = brica1.Agent(s)
ca.add_submodule("mod", mod)
for _ in xrange(16):
ca.step()
ca.step()
ca.step()
mfcc['target'] = mfcc['target'].astype(np.int32)
#concat mfcc,img
#data 1800
N_train = 1500
x_train, x_test = np.split(mfcc['data'], [N_train])
y_train, y_test = np.split(mfcc['target'], [N_train])
N_test = y_test.size
component1 = AutoencoderComponent(117, 80)
component2 = AutoencoderComponent(80, 60)
component3 = AutoencoderComponent(60, lstm_n_units)
LSTMcomponent = LSTMComponent(lstm_n_units, lstm_n_units, 10)
brica1.connect((component1, "output"), (component2, "input"))
brica1.connect((component2, "output"), (component3, "input"))
brica1.connect((component3, "output"), (LSTMcomponent, "input"))
stacked_autoencoder = brica1.ComponentSet()
stacked_autoencoder.add_component("component1", component1, 1)
stacked_autoencoder.add_component("component2", component2, 2)
stacked_autoencoder.add_component("component3", component3, 3)
stacked_autoencoder.add_component("LSTMcomponent", LSTMcomponent, 4)
stacked_autoencoder.make_in_port("input", 117)
stacked_autoencoder.make_in_port("target", 1)
stacked_autoencoder.make_in_port("state_c1", lstm_n_units)
stacked_autoencoder.make_in_port("state_h1", lstm_n_units)
stacked_autoencoder.make_in_port("state_c2", lstm_n_units)
convolutional1 = ConvolutionalAutoencoderComponent(3, 64, 3, stride=1, pad=1, use_gpu=use_gpu)
convolutional2 = ConvolutionalAutoencoderComponent(64, 64, 3, stride=1, pad=1, use_gpu=use_gpu)
poolinganddropout1 = PoolingAndDropout(4096, 4096)
convolutional3 = ConvolutionalAutoencoderComponent(64, 128, 3, stride=1, pad=1, use_gpu=use_gpu)
convolutional4 = ConvolutionalAutoencoderComponent(128, 128, 3, stride=1, pad=1, use_gpu=use_gpu)
poolinganddropout2 = PoolingAndDropout(4096, 4096)
convolutional5 = ConvolutionalAutoencoderComponent(128, 256, 3, stride=1, pad=1, use_gpu=use_gpu)
convolutional6 = ConvolutionalAutoencoderComponent(256, 256, 3, stride=1, pad=1, use_gpu=use_gpu)
convolutional7 = ConvolutionalAutoencoderComponent(256, 256, 3, stride=1, pad=1, use_gpu=use_gpu)
convolutional8 = ConvolutionalAutoencoderComponent(256, 256, 3, stride=1, pad=1, use_gpu=use_gpu)
poolinganddropout3 = PoolingAndDropout(4096, 4096)
autoencoder1 = AutoencoderComponent(4096, 1024, use_gpu=use_gpu)
autoencoder2 = AutoencoderComponent(1024, 1024, use_gpu=use_gpu)
slp = SLPComponent(1024, 4, use_gpu=use_gpu)
brica1.connect((convolutional1, "output"), (convolutional2, "input"))
brica1.connect((convolutional2, "output"), (poolinganddropout1, "input"))
brica1.connect((poolinganddropout1, "output"), (convolutional3, "input"))
brica1.connect((convolutional3, "output"), (convolutional4, "input"))
brica1.connect((convolutional4, "output"), (poolinganddropout2, "input"))
brica1.connect((poolinganddropout2, "output"), (convolutional5, "input"))
brica1.connect((convolutional5, "output"), (convolutional6, "input"))
brica1.connect((convolutional6, "output"), (convolutional7, "input"))
brica1.connect((convolutional7, "output"), (convolutional8, "input"))
brica1.connect((convolutional8, "output"), (poolinganddropout3, "input"))
brica1.connect((poolinganddropout3, "output"), (autoencoder1, "input"))
brica1.connect((autoencoder1, "output"), (autoencoder2, "input"))
brica1.connect((autoencoder2, "output"), (slp, "input"))
stacked_autoencoder = brica1.ComponentSet()
stacked_autoencoder.add_component("convolutional1", convolutional1, 1)
# Setup data feeder component
feeder = brica1.ConstantComponent()
feeder.make_out_port("out0", 2)
# Setup components
svm = SVMComponent(2)
svm.fit(X, y)
RFC = RandomForestClassifierComponent(2)
RFC.fit(X,y)
SR =SVMvsRFC_Component(1)
# Connect the components
brica1.connect((feeder, "out0"), (svm, "in0"))
brica1.connect((feeder, "out0"), (RFC, "in0"))
brica1.connect((svm, "out0"), (SR, "in0"))
brica1.connect((RFC, "out0"), (SR, "in1"))
# Add components to module
mod = brica1.Module()
mod.add_component("feeder", feeder)
mod.add_component("svm", svm)
mod.add_component("RFC",RFC)
mod.add_component("SR", SR)
# Setup scheduler and agent
s = brica1.VirtualTimeSyncScheduler()
a = brica1.Agent(s)
a.add_submodule("mod", mod)
def test_callback(self):
s = brica1.VirtualTimeScheduler()
agent = brica1.Agent(s)
zero = numpy.zeros(3, dtype=numpy.short)
v = numpy.array([1, 2, 3], dtype=numpy.short)
CompA = brica1.ConstantComponent()
CompB = brica1.PipeComponent()
CompC = brica1.NullComponent()
CompA.offset = 2.0
CompB.offset = 0.0
CompC.offset = 1.0
CompA.interval = 5.0
CompB.interval = 5.0
CompC.interval = 5.0
ModA = brica1.Module()
ModA.add_component("CompA", CompA)
ModA.add_component("CompB", CompB)
ModA.add_component("CompC", CompC)
CompA.set_state("out", v)
CompA.make_out_port("out", 3)
CompB.make_in_port("in", 3)
brica1.connect((CompA, "out"), (CompB, "in"))
CompB.make_out_port("out", 3)
CompB.set_map("in", "out")
CompC.make_in_port("in", 3)
brica1.connect((CompB, "out"), (CompC, "in"))
agent.add_submodule("ModA", ModA)
def assign_callback(port):
def callback(v):
self.assertTrue((port.buffer == v).all())
port.register_callback(callback)
assign_callback(CompA.get_out_port("out"))
assign_callback(CompB.get_in_port("in"))
assign_callback(CompB.get_out_port("out"))
assign_callback(CompC.get_in_port("in"))
self.assertTrue((CompA.get_state("out") == v).all())
self.assertIsNot(CompA.get_state("out"), v)
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 5.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 6.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 7.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 10.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 11.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 12.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == v ).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 15.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == v ).all())
self.assertTrue((CompC.get_in_port("in").buffer == v ).all())
self.assertEquals(time, 16.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
self.assertEquals(time, 17.0)
motor_comp = MotorAreaComponent()
hipp_comp = HippocampusComponent()
CompSet = brica1.ComponentSet()
CompSet.add_component("visual_area_component", visual_comp, 0)
CompSet.add_component("hippocampus_component", hipp_comp, 1)
CompSet.add_component("motor_area_component", motor_comp, 2)
main_module = brica1.Module()
main_module.add_component("component_set", CompSet)
# visual to hippocampus
visual_comp.set_state("out_body_position", np.zeros(2, dtype=np.short))
visual_comp.make_out_port("out_body_position", 2)
hipp_comp.make_in_port("in_body_position", 2)
brica1.connect((visual_comp, "out_body_position"), (hipp_comp, "in_body_position"))
# visual to motor
motor_comp.make_in_port("in_body_position", 2)
brica1.connect((visual_comp, "out_body_position"), (motor_comp, "in_body_position"))
visual_comp.set_state("out_body_velocity", np.zeros(2, dtype=np.float32))
visual_comp.make_out_port("out_body_velocity", 2)
motor_comp.make_in_port("in_body_velocity", 2)
brica1.connect((visual_comp, "out_body_velocity"), (motor_comp, "in_body_velocity"))
visual_comp.set_state("out_body_orientation", np.zeros(4, dtype=np.float32))
visual_comp.make_out_port("out_body_orientation", 4)
motor_comp.make_in_port("in_body_orientation", 4)
brica1.connect((visual_comp, "out_body_orientation"), (motor_comp, "in_body_orientation"))
# hippocampus to motor
hipp_comp.set_state("out_target_position", np.zeros(2, dtype=np.short))
mnist = data.load_mnist_data()
mnist['data'] = mnist['data'].astype(np.float32)
mnist['data'] /= 255
mnist['target'] = mnist['target'].astype(np.int32)
N_train = 60000
x_train, x_test = np.split(mnist['data'], [N_train])
y_train, y_test = np.split(mnist['target'], [N_train])
N_test = y_test.size
autoencoder1 = AutoencoderComponent(28**2, 1000, use_gpu=use_gpu)
autoencoder2 = AutoencoderComponent(1000, 1000, use_gpu=use_gpu)
autoencoder3 = AutoencoderComponent(1000, 1000, use_gpu=use_gpu)
slp = SLPComponent(1000, 10)
brica1.connect((autoencoder1, "output"), (autoencoder2, "input"))
brica1.connect((autoencoder2, "output"), (autoencoder3, "input"))
brica1.connect((autoencoder3, "output"), (slp, "input"))
stacked_autoencoder = brica1.ComponentSet()
stacked_autoencoder.add_component("autoencoder1", autoencoder1, 1)
stacked_autoencoder.add_component("autoencoder2", autoencoder2, 2)
stacked_autoencoder.add_component("autoencoder3", autoencoder3, 3)
stacked_autoencoder.add_component("slp", slp, 4)
stacked_autoencoder.make_in_port("input", 28**2)
stacked_autoencoder.make_in_port("target", 1)
stacked_autoencoder.make_out_port("output", 1000)
stacked_autoencoder.make_out_port("loss1", 1)
stacked_autoencoder.make_out_port("loss2", 1)
stacked_autoencoder.make_out_port("loss3", 1)
def test_module(self):
s = brica1.VirtualTimeScheduler()
ca = brica1.Agent(s)
zero = numpy.zeros(3, dtype=numpy.short)
v = numpy.array([1, 2, 3], dtype=numpy.short)
CompA = brica1.ConstantComponent()
CompB = brica1.PipeComponent()
CompC = brica1.NullComponent()
CompA.offset = 2.0
CompB.offset = 0.0
CompC.offset = 1.0
CompA.interval = 5.0
CompB.interval = 5.0
CompC.interval = 5.0
ModA = brica1.Module()
ModB = brica1.Module()
ModC = brica1.Module()
ModD = brica1.Module()
CompA.set_state("out", v)
CompA.make_out_port("out", 3)
CompB.make_in_port("in", 3)
CompB.make_out_port("out", 3)
CompB.set_map("in", "out")
CompC.make_in_port("in", 3)
ModA.make_out_port("out", 3)
ModB.make_in_port("in", 3)
ModB.make_out_port("out", 3)
ModC.make_in_port("in", 3)
ModA.add_component("CompA", CompA)
ModB.add_component("CompB", CompB)
ModC.add_component("CompC", CompC)
brica1.alias_out_port((ModA, "out"), (CompA, "out"))
brica1.alias_in_port((ModB, "in"), (CompB, "in"))
brica1.alias_out_port((ModB, "out"), (CompB, "out"))
brica1.alias_in_port((ModC, "in"), (CompC, "in"))
brica1.connect((ModA, "out"), (ModB, "in"))
brica1.connect((ModB, "out"), (ModC, "in"))
ModD.add_submodule("ModA", ModA)
ModD.add_submodule("ModB", ModB)
ModD.add_submodule("ModC", ModC)
ca.add_submodule("ModD", ModD)
self.assertTrue((CompA.get_state("out") == v).all())
self.assertIsNot(CompA.get_state("out"), v)
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 5.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 6.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 7.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 10.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 11.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 12.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == v ).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == v ).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 15.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
self.assertTrue((ModA.get_out_port("out").buffer == v).all())
self.assertTrue((ModB.get_in_port("in").buffer == v).all())
self.assertTrue((ModB.get_out_port("out").buffer == v).all())
self.assertTrue((ModC.get_in_port("in").buffer == v).all())
self.assertEquals(time, 16.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
self.assertTrue((ModA.get_out_port("out").buffer == v).all())
self.assertTrue((ModB.get_in_port("in").buffer == v).all())
self.assertTrue((ModB.get_out_port("out").buffer == v).all())
self.assertTrue((ModC.get_in_port("in").buffer == v).all())
self.assertEquals(time, 17.0)
s = brica1.VirtualTimeScheduler()
ca = brica1.Agent(s)
cycles = 24000
sensor = MNISTSensor()
da1 = DAComponent(784, 1000, use_cuda=use_gpu, max_cycles=cycles)
da2 = DAComponent(1000, 1000, use_cuda=use_gpu, max_cycles=cycles)
da3 = DAComponent(1000, 1000, use_cuda=use_gpu, max_cycles=cycles)
perceptron = PerceptronComponent(1000,
10,
use_cuda=use_gpu,
max_cycles=cycles)
sda = brica1.ComponentSet()
brica1.connect((da1, "out"), (da2, "in"))
brica1.connect((da2, "out"), (da3, "in"))
sda.add_component("da1", da1, 0)
sda.add_component("da2", da2, 1)
sda.add_component("da3", da3, 2)
sda.make_in_port("x_in", 784)
sda.make_in_port("y_in", 1)
sda.make_out_port("out", 1)
brica1.connect((sensor, "x_train"), (da1, "in"))
brica1.connect((da1, "out"), (da2, "in"))
brica1.connect((da2, "out"), (da3, "in"))
brica1.connect((da3, "out"), (perceptron, "x_in"))
brica1.connect((sensor, "y_train"), (perceptron, "y_in"))
sda = brica1.ComponentSet()
def check_consistency(self):
"""
Args:
None
return:
true iff no fatal inconsistency in the network
function:
see the consistency check section below.
"""
for module_name in self.module_dictionary:
if not module_name in self.unit_dic:
if debug:
print "Creating " + module_name + "."
self.unit_dic[module_name]=brica1.Module() # New Module instance
# SuperModules of consistency check
for module, superModule in self.super_modules.items():
if not superModule in self.module_dictionary:
print >> sys.stderr, "ERROR: Super Module '%s' is not defined!" % (superModule)
return False
# Loop check
if self.__loop_check(superModule, module):
print >> sys.stderr, "ERROR: Loop detected while trying to add " + module + " as a subunit to " + superModule + "!"
return False
# SubModules of consistency check
for superModule, subModules in self.sub_modules.items():
for subModule in subModules:
if not subModule in self.module_dictionary:
print >> sys.stderr, "ERROR: Sub Module '%s' is not defined!" % (subModule)
return False
# Loop check
if self.__loop_check(superModule, subModule):
print >> sys.stderr, "ERROR: Loop detected while trying to add " + superModule + " as a subunit to " + subModule + "!"
return False
# Port of consistency check
for module_name in self.module_dictionary:
ports = self.module_dictionary[module_name]["Ports"]
if len(ports) == 0:
print >> sys.stderr, "ERROR: The specified module '%s' does not have the port!" % module_name
return False
for port in ports:
if not module_name + "." + port in self.__ports:
print >> sys.stderr, "ERROR: The specified module '%s' does not have the port!" % module_name
return False
for port_name, v in self.__ports.items():
# Fatal if the specified modules have not been defined.
if not "Module" in v:
print >> sys.stderr, "ERROR: Module is not defined in the port '%s'!" % port_name
return False
module_name = v["Module"]
if not module_name in self.module_dictionary:
print >> sys.stderr, "ERROR: Specified module '%s' is not defined in the port '%s'!" % (module_name, port_name)
return False
# Fatal if the shape has not been defined.
if not "Shape" in v:
print >> sys.stderr, "ERROR: Shape is not defined in the port '%s'!" % port_name
return False
length = v["Shape"]
if length < 1:
print >> sys.stderr, "ERROR: Incorrect length of Shape for the port '%s'!" % port_name
return False
# Fatal if the specified modules do not have the port, abort with a message.
module = self.module_dictionary[module_name]
pv = port_name.split(".")
last_port_name = pv[len(pv) - 1]
if not last_port_name in module["Ports"]:
print >> sys.stderr, "ERROR: Port '%s' is not defined in the module '%s'!" % (last_port_name, module_name)
return False
module = self.unit_dic[module_name]
if v["IO"] == "Input":
module.make_in_port(last_port_name, length)
if debug:
print "Creating an input port " + last_port_name + " (length " + str(length) + ") to " + module_name + "."
elif v["IO"] == "Output":
module.make_out_port(last_port_name, length)
if debug:
print "Creating an output port " + last_port_name + " (length " + str(length) + ") to " + module_name + "."
# Connection of consistency check
for k, v in self.__connections.items():
# Fatal if the specified ports have not been defined.
if not v[0] in self.__ports:
print >> sys.stderr, "ERROR: The specified port '%s' is not defined in connection '%s'." % (v[0], k)
return False
if not v[1] in self.__ports:
print >> sys.stderr, "ERROR: The specified port '%s' is not defined in connection '%s'." % (v[1], k)
return False
tp = v[0].split(".")
to_port = tp[len(tp) - 1]
fp = v[1].split(".")
from_port = fp[len(fp) - 1]
to_unit = self.__ports[v[0]]["Module"]
from_unit = self.__ports[v[1]]["Module"]
# if from_unit & to_unit belong to the same level
if ((not from_unit in self.__super_sub_modules) and (not to_unit in self.__super_sub_modules)) or \
(from_unit in self.__super_sub_modules and to_unit in self.__super_sub_modules and \
(self.__super_sub_modules[from_unit] == self.__super_sub_modules[to_unit])):
try:
fr_port_obj = self.unit_dic[from_unit].get_out_port(from_port)
to_port_obj = self.unit_dic[to_unit].get_in_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
print >> sys.stderr, "ERROR: Port dimension unmatch!"
return False
# Creating a connection
brica1.connect((self.unit_dic[from_unit],from_port), (self.unit_dic[to_unit],to_port))
if debug:
print "Creating a connection from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "."
except:
print >> sys.stderr, "ERROR: adding a connection from " + from_unit + " to " + to_unit + " on the same level but not from an output port to an input port!"
return False
# else if from_unit is the direct super module of the to_unit
elif to_unit in self.__super_sub_modules and self.__super_sub_modules[to_unit]==from_unit:
try:
fr_port_obj = self.unit_dic[from_unit].get_in_port(from_port)
to_port_obj = self.unit_dic[to_unit].get_in_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
print >> sys.stderr, "ERROR: Port dimension unmatch!"
return False
# Creating a connection (alias)
self.unit_dic[to_unit].alias_in_port(self.unit_dic[from_unit], from_port, to_port)
if debug:
print "Creating a connection (alias) from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "."
except:
print >> sys.stderr, "ERROR: Error adding a connection from the super module " + from_unit + " to " + to_unit + " but not from an input port to an input port!"
return False
# else if to_unit is the direct super module of the from_unit
elif from_unit in self.__super_sub_modules and self.__super_sub_modules[from_unit]==to_unit:
try:
fr_port_obj = self.unit_dic[from_unit].get_out_port(from_port)
to_port_obj = self.unit_dic[to_unit].get_out_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
print >> sys.stderr, "ERROR: Port dimension unmatch!"
return False
# Creating a connection (alias)
self.unit_dic[from_unit].alias_out_port(self.unit_dic[to_unit], to_port, from_port)
if debug:
print "Creating a connection (alias) from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "."
except:
print >> sys.stderr, "ERROR: Error adding a connection from " + from_unit + " to its super module " + to_unit + " but not from an output port to an output port!"
return False
# else connection level error!
else:
print >> sys.stderr, "ERROR: Trying to add a connection between units " + from_unit + " and " + to_unit + " in a remote level!"
return False
return True
def __add_a_connection(self, connection):
# TODO: Port length check
try:
connection_name = connection["Name"]
except KeyError:
print >> sys.stderr, "Name not specified while adding a connection!"
return
try:
from_unit = connection["FromModule"]
from_unit = self.__prefix_base_name_space(from_unit)
except KeyError:
print >> sys.stderr, "FromModule not specified while adding a connection!"
return
try:
from_port = connection["FromPort"]
except KeyError:
print >> sys.stderr, "FromPort not specified while adding a connection!"
return
try:
to_unit = connection["ToModule"]
to_unit = self.__prefix_base_name_space(to_unit)
except KeyError:
print >> sys.stderr, "ToModule not specified while adding a connection!"
return
try:
to_port = connection["ToPort"]
except KeyError:
print >> sys.stderr, "ToPort not specified while adding a connection!"
return
# Checking if the modules have been defined.
if not from_unit in self.__unit_dic:
print >> sys.stderr, "Module " + from_unit + " not defined!"
return
if not to_unit in self.__unit_dic:
print >> sys.stderr, "Module " + to_unit + " not defined!"
return
# if from_unit & to_unit belong to the same level
if ((not from_unit in self.__super_modules) and (not to_unit in self.__super_modules)) or \
(from_unit in self.__super_modules and to_unit in self.__super_modules and (self.__super_modules[from_unit] == self.__super_modules[to_unit])):
try:
fr_port_obj = self.__unit_dic[from_unit].get_out_port(
from_port)
to_port_obj = self.__unit_dic[to_unit].get_in_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
print >> sys.stderr, "Port dimension unmatch!"
raise Error
# Creating a connection
brica1.connect((self.__unit_dic[from_unit], from_port),
(self.__unit_dic[to_unit], to_port))
print "Creating a connection from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "."
except Error:
print >> sys.stderr, "Error adding a connection from " + from_unit + " to " + to_unit + " on the same level but not from an output port to an input port!"
return
# else if from_unit is the direct super module of the to_unit
elif to_unit in self.__super_modules and self.__super_modules[
to_unit] == from_unit:
try:
fr_port_obj = self.__unit_dic[from_unit].get_in_port(from_port)
to_port_obj = self.__unit_dic[to_unit].get_in_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
print >> sys.stderr, "Port dimension unmatch!"
raise Error
# Creating a connection (alias)
self.__unit_dic[to_unit].alias_in_port(
self.__unit_dic[from_unit], from_port, to_port)
print "Creating a connection (alias) from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "."
except Error:
print >> sys.stderr, "Error adding a connection from the super module " + from_unit + " to " + to_unit + " but not from an input port to an input port!"
return
# else if to_unit is the direct super module of the from_unit
elif from_unit in self.__super_modules and self.__super_modules[
from_unit] == to_unit:
try:
fr_port_obj = self.__unit_dic[from_unit].get_out_port(
from_port)
to_port_obj = self.__unit_dic[to_unit].get_out_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
print >> sys.stderr, "Port dimension unmatch!"
raise Error
# Creating a connection (alias)
self.__unit_dic[from_unit].alias_out_port(
self.__unit_dic[to_unit], to_port, from_port)
print "Creating a connection (alias) from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "."
except KeyError:
print >> sys.stderr, "Error adding a connection from " + from_unit + " to its super module " + to_unit + " but not from an output port to an output port!"
return
# else connection level error!
else:
print >> sys.stderr, "Trying to add a connection between units " + from_unit + " and " + to_unit + " in a remote level!"
return
# Load iris dataset
iris = datasets.load_iris()
X = iris.data[:, :2]
y = iris.target
# Setup data feeder component
feeder = brica1.ConstantComponent()
feeder.make_out_port("out0", 2)
# Setup SVM component
svm = SVMComponent(2)
svm.fit(X, y)
# Connect the components
brica1.connect((feeder, "out0"), (svm, "in0"))
# Add components to module
mod = brica1.Module()
mod.add_component("feeder", feeder)
mod.add_component("svm", svm)
# Setup scheduler and agent
s = brica1.VirtualTimeSyncScheduler()
a = brica1.Agent(s)
a.add_submodule("mod", mod)
# Test the classifier
for i in xrange(len(X)):
feeder.set_state("out0", X[i]) # Set data feeder to training data i
# Load iris dataset
iris = datasets.load_iris()
X = iris.data[:, :2]
y = iris.target
# Setup data feeder component
feeder = brica1.ConstantComponent()
feeder.make_out_port("out0", 2)
# Setup SVM component
svm = SVMComponent(2)
svm.fit(X, y)
# Connect the components
brica1.connect((feeder, "out0"), (svm, "in0"))
# Add components to module
mod = brica1.Module()
mod.add_component("feeder", feeder)
mod.add_component("svm", svm)
# Setup scheduler and agent
s = brica1.VirtualTimeSyncScheduler()
a = brica1.Agent(s)
a.add_submodule("mod", mod)
# Test the classifier
for i in xrange(len(X)):
feeder.set_state("out0", X[i]) # Set data feeder to training data i
def test_nested(self):
s = brica1.VirtualTimeScheduler()
agent = brica1.Agent(s)
zero = numpy.zeros(3, dtype=numpy.short)
v = numpy.array([1, 2, 3], dtype=numpy.short)
CompA = brica1.ConstantComponent()
CompB = brica1.PipeComponent()
CompC = brica1.NullComponent()
CompA.offset = 2.0
CompB.offset = 0.0
CompC.offset = 1.0
CompA.interval = 5.0
CompB.interval = 5.0
CompC.interval = 5.0
ModA = brica1.Module()
ModB = brica1.Module()
ModC = brica1.Module()
SupA = brica1.Module()
SupB = brica1.Module()
SupC = brica1.Module()
Top = brica1.Module()
CompA.set_state("out", v)
CompA.make_out_port("out", 3)
CompB.make_in_port("in", 3)
CompB.make_out_port("out", 3)
CompB.set_map("in", "out")
CompC.make_in_port("in", 3)
ModA.make_out_port("out", 3)
ModB.make_in_port("in", 3)
ModB.make_out_port("out", 3)
ModC.make_in_port("in", 3)
SupA.make_out_port("out", 3)
SupB.make_in_port("in", 3)
SupB.make_out_port("out", 3)
SupC.make_in_port("in", 3)
SupA.add_submodule("ModA", ModA)
SupB.add_submodule("ModB", ModB)
SupC.add_submodule("ModC", ModC)
ModA.add_component("CompA", CompA)
ModB.add_component("CompB", CompB)
ModC.add_component("CompC", CompC)
# Port aliasing must start from outside-in
brica1.alias_out_port((SupA, "out"), (ModA, "out"))
brica1.alias_out_port((ModA, "out"), (CompA, "out"))
brica1.alias_in_port((SupB, "in"), (ModB, "in"))
brica1.alias_in_port((ModB, "in"), (CompB, "in"))
brica1.alias_out_port((SupB, "out"), (ModB, "out"))
brica1.alias_out_port((ModB, "out"), (CompB, "out"))
brica1.alias_in_port((SupC, "in"), (ModC, "in"))
brica1.alias_in_port((ModC, "in"), (CompC, "in"))
brica1.connect((SupA, "out"), (SupB, "in"))
brica1.connect((SupB, "out"), (SupC, "in"))
Top.add_submodule("SupA", SupA)
Top.add_submodule("SupB", SupB)
Top.add_submodule("SupC", SupC)
agent.add_submodule("Top", Top)
self.assertTrue((CompA.get_state("out") == v).all())
self.assertIsNot(CompA.get_state("out"), v)
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == zero).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == zero).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 5.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == zero).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 6.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 7.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 10.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 11.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 12.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == v ).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == v ).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == v ).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 15.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
self.assertTrue((ModA.get_out_port("out").buffer == v).all())
self.assertTrue((ModB.get_in_port("in").buffer == v).all())
self.assertTrue((ModB.get_out_port("out").buffer == v).all())
self.assertTrue((ModC.get_in_port("in").buffer == v).all())
self.assertTrue((SupA.get_out_port("out").buffer == v).all())
self.assertTrue((SupB.get_in_port("in").buffer == v).all())
self.assertTrue((SupB.get_out_port("out").buffer == v).all())
self.assertTrue((SupC.get_in_port("in").buffer == v).all())
self.assertEquals(time, 16.0)
time = agent.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
self.assertTrue((ModA.get_out_port("out").buffer == v).all())
self.assertTrue((ModB.get_in_port("in").buffer == v).all())
self.assertTrue((ModB.get_out_port("out").buffer == v).all())
self.assertTrue((ModC.get_in_port("in").buffer == v).all())
self.assertTrue((SupA.get_out_port("out").buffer == v).all())
self.assertTrue((SupB.get_in_port("in").buffer == v).all())
self.assertTrue((SupB.get_out_port("out").buffer == v).all())
self.assertTrue((SupC.get_in_port("in").buffer == v).all())
self.assertEquals(time, 17.0)
mnist = data.load_mnist_data()
mnist['data'] = mnist['data'].astype(np.float32)
mnist['data'] /= 255
mnist['target'] = mnist['target'].astype(np.int32)
N_train = 60000
x_train, x_test = np.split(mnist['data'], [N_train])
y_train, y_test = np.split(mnist['target'], [N_train])
N_test = y_test.size
autoencoder1 = AutoencoderComponent(28**2, 1000, use_gpu=use_gpu)
autoencoder2 = AutoencoderComponent(1000, 1000, use_gpu=use_gpu)
autoencoder3 = AutoencoderComponent(1000, 1000, use_gpu=use_gpu)
slp = SLPComponent(1000, 10)
brica1.connect((autoencoder1, "output"), (autoencoder2, "input"))
brica1.connect((autoencoder2, "output"), (autoencoder3, "input"))
brica1.connect((autoencoder3, "output"), (slp, "input"))
stacked_autoencoder = brica1.ComponentSet()
stacked_autoencoder.add_component("autoencoder1", autoencoder1, 1)
stacked_autoencoder.add_component("autoencoder2", autoencoder2, 2)
stacked_autoencoder.add_component("autoencoder3", autoencoder3, 3)
stacked_autoencoder.add_component("slp", slp, 4)
stacked_autoencoder.make_in_port("input", 28**2)
stacked_autoencoder.make_in_port("target", 1)
stacked_autoencoder.make_out_port("output", 1000)
stacked_autoencoder.make_out_port("loss1", 1)
stacked_autoencoder.make_out_port("loss2", 1)
stacked_autoencoder.make_out_port("loss3", 1)
# Setup data feeder component
feeder = brica1.ConstantComponent()
feeder.make_out_port("out0", 2)
# Setup components
svm = SVMComponent(2)
svm.fit(X, y)
RFC = RandomForestClassifierComponent(2)
RFC.fit(X, y)
SR = SVMvsRFC_Component(1)
# Connect the components
brica1.connect((feeder, "out0"), (svm, "in0"))
brica1.connect((feeder, "out0"), (RFC, "in0"))
brica1.connect((svm, "out0"), (SR, "in0"))
brica1.connect((RFC, "out0"), (SR, "in1"))
# Add components to module
mod = brica1.Module()
mod.add_component("feeder", feeder)
mod.add_component("svm", svm)
mod.add_component("RFC", RFC)
mod.add_component("SR", SR)
# Setup scheduler and agent
s = brica1.VirtualTimeSyncScheduler()
a = brica1.Agent(s)
a.add_submodule("mod", mod)
num.offset = 0.0
cnn.offset = 1.0
rnn.offset = 2.0
num.interval = 3.0
cnn.interval = 3.0
rnn.interval = 3.0
mod = brica1.Module()
mod.add_component("num", num)
mod.add_component("cnn", cnn)
mod.add_component("rnn", rnn)
num.make_out_port("out", 1)
cnn.make_in_port("in", 1)
cnn.make_out_port("out", 1)
rnn.make_in_port("in", 1)
brica1.connect((num, "out"), (cnn, "in"))
brica1.connect((cnn, "out"), (rnn, "in"))
s = brica1.VirtualTimeScheduler()
ca = brica1.Agent(s)
ca.add_submodule("mod", mod)
for _ in xrange(16):
ca.step()
ca.step()
ca.step()
3,
stride=1,
pad=1,
use_gpu=use_gpu)
convolutional8 = ConvolutionalAutoencoderComponent(256,
256,
3,
stride=1,
pad=1,
use_gpu=use_gpu)
poolinganddropout3 = PoolingAndDropout(4096, 4096)
autoencoder1 = AutoencoderComponent(4096, 1024, use_gpu=use_gpu)
autoencoder2 = AutoencoderComponent(1024, 1024, use_gpu=use_gpu)
slp = SLPComponent(1024, 4, use_gpu=use_gpu)
brica1.connect((convolutional1, "output"), (convolutional2, "input"))
brica1.connect((convolutional2, "output"), (poolinganddropout1, "input"))
brica1.connect((poolinganddropout1, "output"), (convolutional3, "input"))
brica1.connect((convolutional3, "output"), (convolutional4, "input"))
brica1.connect((convolutional4, "output"), (poolinganddropout2, "input"))
brica1.connect((poolinganddropout2, "output"), (convolutional5, "input"))
brica1.connect((convolutional5, "output"), (convolutional6, "input"))
brica1.connect((convolutional6, "output"), (convolutional7, "input"))
brica1.connect((convolutional7, "output"), (convolutional8, "input"))
brica1.connect((convolutional8, "output"), (poolinganddropout3, "input"))
brica1.connect((poolinganddropout3, "output"), (autoencoder1, "input"))
brica1.connect((autoencoder1, "output"), (autoencoder2, "input"))
brica1.connect((autoencoder2, "output"), (slp, "input"))
stacked_autoencoder = brica1.ComponentSet()
stacked_autoencoder.add_component("convolutional1", convolutional1, 1)
def check_consistency(self):
"""
Args:
None
return:
true iff no fatal inconsistency in the network
function:
see the consistency check section below.
"""
for module_name in self.module_dictionary:
if module_name not in self.unit_dic:
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug("Creating {}.".format(module_name))
self.unit_dic[module_name] = brica1.Module(
) # New Module instance
# SuperModules of consistency check
for module, superModule in self.super_modules.items():
if superModule not in self.module_dictionary:
app_logger.error(
"Super Module {} is not defined!".format(superModule))
return False
# Loop check
if self.__loop_check(superModule, module):
app_logger.error(
"Loop detected while trying to add {} as a subunit to {}!".
format(module, superModule))
return False
# SubModules of consistency check
for superModule, subModules in self.sub_modules.items():
for subModule in subModules:
if subModule not in self.module_dictionary:
app_logger.error(
"Sub Module {} is not defined!".format(subModule))
return False
# Loop check
if self.__loop_check(superModule, subModule):
app_logger.error(
"Loop detected while trying to add {} as a subunit to {}!"
.format(superModule, subModule))
return False
# Port of consistency check
for module_name in self.module_dictionary:
ports = self.module_dictionary[module_name]["Ports"]
if len(ports) == 0:
app_logger.error(
"The specified module {} does not have the port!".format(
module_name))
return False
for port in ports:
if not module_name + "." + port in self.__ports:
app_logger.error(
"The specified module {} does not have the port!".
format(module_name))
return False
for port_name, v in self.__ports.items():
# Fatal if the specified modules have not been defined.
if "Module" not in v:
app_logger.error(
"Module is not defined in the port {}!".format(port_name))
return False
module_name = v["Module"]
if module_name not in self.module_dictionary:
app_logger.error(
"Specified module {} is not defined in the port {}!".
format(module_name, port_name))
return False
# Fatal if the shape has not been defined.
if "Shape" not in v:
app_logger.error(
"Shape is not defined in the port {}!".format(port_name))
return False
length = v["Shape"]
if length < 1:
app_logger.error(
"Incorrect length of Shape for the port {}!".format(
port_name))
return False
# Fatal if the specified modules do not have the port, abort with a message.
module = self.module_dictionary[module_name]
pv = port_name.split(".")
last_port_name = pv[len(pv) - 1]
if last_port_name not in module["Ports"]:
app_logger.error(
"Port {} is not defined in the module {}!".format(
last_port_name, module_name))
return False
module = self.unit_dic[module_name]
if v["IO"] == "Input":
module.make_in_port(last_port_name, length)
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating an input port {} (length {}) to {}.".format(
last_port_name, length, module_name))
elif v["IO"] == "Output":
module.make_out_port(last_port_name, length)
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating an output port {} (length {}) to {}.".format(
last_port_name, length, module_name))
# Connection of consistency check
for k, v in self.__connections.items():
# Fatal if the specified ports have not been defined.
if not v[0] in self.__ports:
app_logger.error(
"The specified port {} is not defined in connection {}.".
format(v[0], k))
return False
if not v[1] in self.__ports:
app_logger.error(
"The specified port {} is not defined in connection {}.".
format(v[1], k))
return False
tp = v[0].split(".")
to_port = tp[len(tp) - 1]
fp = v[1].split(".")
from_port = fp[len(fp) - 1]
to_unit = self.__ports[v[0]]["Module"]
from_unit = self.__ports[v[1]]["Module"]
# if from_unit & to_unit belong to the same level
if ((from_unit not in self.__super_sub_modules) and (to_unit not in self.__super_sub_modules)) or \
(from_unit in self.__super_sub_modules and to_unit in self.__super_sub_modules and (
self.__super_sub_modules[from_unit] == self.__super_sub_modules[to_unit])):
try:
fr_port_obj = self.unit_dic[from_unit].get_out_port(
from_port)
to_port_obj = self.unit_dic[to_unit].get_in_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
app_logger.error("Port dimension unmatch!")
return False
# Creating a connection
brica1.connect((self.unit_dic[from_unit], from_port),
(self.unit_dic[to_unit], to_port))
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating a connection from {} of {} to {} of {}".
format(from_port, from_unit, to_port, to_unit))
except:
app_logger.error(
"adding a connection from {} to {} on the same level"
" but not from an output port to an input port!".
format(from_unit, to_unit))
return False
# else if from_unit is the direct super module of the to_unit
elif to_unit in self.__super_sub_modules and self.__super_sub_modules[
to_unit] == from_unit:
try:
fr_port_obj = self.unit_dic[from_unit].get_in_port(
from_port)
to_port_obj = self.unit_dic[to_unit].get_in_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
app_logger.error("Port dimension unmatch!")
return False
# Creating a connection (alias)
self.unit_dic[to_unit].alias_in_port(
self.unit_dic[from_unit], from_port, to_port)
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating a connection (alias) from {} of {} to {} of {}."
.format(from_port, from_unit, to_port, to_unit))
except:
app_logger.error(
"Error adding a connection from the super module {} to {} "
"but not from an input port to an input port!".format(
from_unit, to_unit))
return False
# else if to_unit is the direct super module of the from_unit
elif from_unit in self.__super_sub_modules and self.__super_sub_modules[
from_unit] == to_unit:
try:
fr_port_obj = self.unit_dic[from_unit].get_out_port(
from_port)
to_port_obj = self.unit_dic[to_unit].get_out_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
app_logger.error("Port dimension unmatch!")
return False
# Creating a connection (alias)
self.unit_dic[from_unit].alias_out_port(
self.unit_dic[to_unit], to_port, from_port)
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating a connection (alias) from {} of {} to {} of {}."
.format(from_port, from_unit, to_port, to_unit))
except:
app_logger.error(
"Error adding a connection from {} to its super module {} "
"but not from an output port to an output port!".
format(from_unit, to_unit))
return False
# else connection level error!
else:
app_logger.error(
"Trying to add a connection between units {} and {} in a remote level!"
.format(from_unit, to_unit))
return False
return True
motor_comp = MotorAreaComponent()
hipp_comp = HippocampusComponent()
CompSet = brica1.ComponentSet()
CompSet.add_component("visual_area_component", visual_comp, 0)
CompSet.add_component("hippocampus_component", hipp_comp, 1)
CompSet.add_component("motor_area_component", motor_comp, 2)
main_module = brica1.Module()
main_module.add_component("component_set", CompSet)
# visual to hippocampus
visual_comp.set_state("out_body_position", np.zeros(2, dtype=np.short))
visual_comp.make_out_port("out_body_position", 2)
hipp_comp.make_in_port("in_body_position", 2)
brica1.connect((visual_comp, "out_body_position"),
(hipp_comp, "in_body_position"))
# visual to motor
motor_comp.make_in_port("in_body_position", 2)
brica1.connect((visual_comp, "out_body_position"),
(motor_comp, "in_body_position"))
visual_comp.set_state("out_body_velocity", np.zeros(2,
dtype=np.float32))
visual_comp.make_out_port("out_body_velocity", 2)
motor_comp.make_in_port("in_body_velocity", 2)
brica1.connect((visual_comp, "out_body_velocity"),
(motor_comp, "in_body_velocity"))
visual_comp.set_state("out_body_orientation",
np.zeros(4, dtype=np.float32))
visual_comp.make_out_port("out_body_orientation", 4)
motor_comp.make_in_port("in_body_orientation", 4)
def __add_a_connection(self, connection): # TODO: Port length check try: connection_name = connection["Name"] except KeyError: print >> sys.stderr, "Name not specified while adding a connection!" return try: from_unit = connection["FromModule"] from_unit = self.__prefix_base_name_space(from_unit) except KeyError: print >> sys.stderr, "FromModule not specified while adding a connection!" return try: from_port = connection["FromPort"] except KeyError: print >> sys.stderr, "FromPort not specified while adding a connection!" return try: to_unit = connection["ToModule"] to_unit = self.__prefix_base_name_space(to_unit) except KeyError: print >> sys.stderr, "ToModule not specified while adding a connection!" return try: to_port = connection["ToPort"] except KeyError: print >> sys.stderr, "ToPort not specified while adding a connection!" return # Checking if the modules have been defined. if not from_unit in self.__unit_dic: print >> sys.stderr, "Module " + from_unit + " not defined!" return if not to_unit in self.__unit_dic: print >> sys.stderr, "Module " + to_unit + " not defined!" return # if from_unit & to_unit belong to the same level if ((not from_unit in self.__super_modules) and (not to_unit in self.__super_modules)) or \ (from_unit in self.__super_modules and to_unit in self.__super_modules and (self.__super_modules[from_unit] == self.__super_modules[to_unit])): try: fr_port_obj = self.__unit_dic[from_unit].get_out_port(from_port) to_port_obj = self.__unit_dic[to_unit].get_in_port(to_port) if fr_port_obj.buffer.shape != to_port_obj.buffer.shape: print >> sys.stderr, "Port dimension unmatch!" raise Error # Creating a connection brica1.connect((self.__unit_dic[from_unit],from_port), (self.__unit_dic[to_unit],to_port)) print "Creating a connection from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "." except Error: print >> sys.stderr, "Error adding a connection from " + from_unit + " to " + to_unit + " on the same level but not from an output port to an input port!" return # else if from_unit is the direct super module of the to_unit elif to_unit in self.__super_modules and self.__super_modules[to_unit]==from_unit: try: fr_port_obj = self.__unit_dic[from_unit].get_in_port(from_port) to_port_obj = self.__unit_dic[to_unit].get_in_port(to_port) if fr_port_obj.buffer.shape != to_port_obj.buffer.shape: print >> sys.stderr, "Port dimension unmatch!" raise Error # Creating a connection (alias) self.__unit_dic[to_unit].alias_in_port(self.__unit_dic[from_unit], from_port, to_port) print "Creating a connection (alias) from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "." except Error: print >> sys.stderr, "Error adding a connection from the super module " + from_unit + " to " + to_unit + " but not from an input port to an input port!" return # else if to_unit is the direct super module of the from_unit elif from_unit in self.__super_modules and self.__super_modules[from_unit]==to_unit: try: fr_port_obj = self.__unit_dic[from_unit].get_out_port(from_port) to_port_obj = self.__unit_dic[to_unit].get_out_port(to_port) if fr_port_obj.buffer.shape != to_port_obj.buffer.shape: print >> sys.stderr, "Port dimension unmatch!" raise Error # Creating a connection (alias) self.__unit_dic[from_unit].alias_out_port(self.__unit_dic[to_unit], to_port, from_port) print "Creating a connection (alias) from " + from_port + " of " + from_unit + " to " + to_port + " of " + to_unit + "." except KeyError: print >> sys.stderr, "Error adding a connection from " + from_unit + " to its super module " + to_unit + " but not from an output port to an output port!" return # else connection level error! else: print >> sys.stderr, "Trying to add a connection between units " + from_unit + " and " + to_unit + " in a remote level!" return
