def connect_through_corner(src, dst, rcorn, ccorn, track=0, dir='hv', DBG=0):
corn = cgra_info.rc2tileno(rcorn, ccorn)
if DBG: print "# Found corner tile %d (r%d,c%d)"\
% (corn, rcorn, ccorn)
# horizontal path from src to corn
if DBG > 1: print "# path1:",
p = connect_tiles(src, corn, track, DBG=0)
(begin1, path1, end1) = unpack_path(p)
if DBG > 1: print "# "
# vert path from corn to dest
if DBG > 1: print "# path2:",
# (begin2,path2,end2) = connect_tiles(corn,dst,track,DBG=DBG-1)
p = connect_tiles(corn, dst, track, DBG=0)
(begin2, path2, end2) = unpack_path(p)
if DBG > 1: print "# "
# In corner tile, connect end1 to begin2
cornerconn = ["%s -> %s" % (end1, begin2)]
if DBG > 1: print "# corner:", cornerconn
if DBG: print "# "
final_path = path1 + cornerconn + path2
if DBG: prettyprint_path(dir, begin1, path1, cornerconn, path2, end2)
return pack_path(begin1, final_path, end2)
def build_wire_rc(r, c, inout, side, track):
tileno = cgra_info.rc2tileno(r, c)
# Need mem offset if row==odd indicates mem tile bottom-half
if is_mem_rc(r, c) and (r % 2 == 1): mo = 4
else: mo = 0
return "T%d_%s_s%dt%d" % (tileno, inout, side + mo, track)
def is_mem_rc(r, c):
tileno = cgra_info.rc2tileno(r, c)
tiletype = cgra_info.tiletype(tileno)
# print "Tile %d has type '%s'" % (tileno,tiletype)
# "return re.search()" DOES NOT WORK! (why?)
if re.search("^mem", tiletype): return True
else: return False
def connect_through_corner(src, dst, rcorn, ccorn, track=0, dir='hv', DBG=0):
# DBG=9
# if (src==18) and (dst==31): print("666d RECURSE NOW?")
# assert False
if DBG > 2:
print(rcorn, ccorn)
print 'src=', src
print 'dst=', dst
corn = cgra_info.rc2tileno(rcorn, ccorn)
if DBG: print "# Found corner tile %d (r%d,c%d)"\
% (corn, rcorn, ccorn)
assert corn > 0
# horizontal (or vert) path from src to corn
p = connect_tiles(src, corn, track, DBG=0)
if DBG > 1: print "# path1:", p
# path1: ['T121_out_s3t4', 'T89_in_s5t4']
(begin1, path1, end1) = unpack_path(p)
if DBG > 1: print "# "
# vert (or horiz) path from corn to dest
# (begin2,path2,end2) = connect_tiles(corn,dst,track,DBG=DBG-1)
p = connect_tiles(corn, dst, track, DBG=0)
if DBG > 1: print "# path2:", p
# path2: ['T89_out_s1t4', 'T89_in_s7t4 -> T89_out_s6t4', 'T106_in_s0t4']
(begin2, path2, end2) = unpack_path(p)
if DBG > 1: print "# "
# In corner tile, connect end1 to begin2
# eg cornerconn = ["%s -> %s"] % (end1,begin2)
# or cornerconn = ["%s -> %s", "%s -> %s"] % (end1,mid1,mid2,begin2)]
cornerconn = find_cornerconn(end1, begin2, DBG=DBG)
final_path = path1 + cornerconn + path2
if DBG: prettyprint_path(dir, begin1, path1, cornerconn, path2, end2)
return pack_path(begin1, final_path, end2)
def find_neighbor(w, DBG=9):
'''E.g. find_neighbor_wire("T4_in_s1t1") => ("T5_out_s3t1")'''
# FIXME this can all be cleaned up...
if (0):
(tilefoo, wfoo) = (3, ("sb_wire_in1_s3t2", "out0_s1t2"))
(tilefoo, wfoo) = (1, ("in_s2t4"))
if (tileno == tilefoo) and (w in wfoo):
DBG = 1
print "\nWant match for tile %d wire '%s'" % (tileno, w)
# # find_neighbor_wire(4,"in_s1t1") => (5, "out_s3t1")
# find_neighbor_wire("T4_in_s1t1") => ("T5_out_s3t1")
#
# parse = re.search("(in|out)([01])*_s([0-9]+)t([0-9]+)", w)
(tileno, dir, side, track) = parsewire(w)
# Only works for 'out' wires (HA!)
assert dir == 'out'
in_or_out = dir
# top_or_bottom = parse.group(2) # 'None', '0' or '1'
top_or_bottom = side / 4 # '0' or '1'
if (in_or_out == "out"): in_or_out = "in"
else: in_or_out = "out"
(r, c) = cgra_info.tileno2rc(tileno)
# Adjust for wire in bottom of a memtile
if (top_or_bottom == '1'): r = r + 1
if (side == 0): (r, c, side) = (r, c + 1, side + 2)
elif (side == 1): (r, c, side) = (r + 1, c, side + 2)
elif (side == 2): (r, c, side) = (r, c - 1, side - 2)
elif (side == 3):
(r, c, side) = (r - 1, c, side - 2)
# Yes, yes, I know
elif (side == 4):
(r, c, side) = (r, c + 1, side + 2)
elif (side == 5):
(r, c, side) = (r + 1, c, side + 2)
elif (side == 6):
(r, c, side) = (r, c - 1, side - 2)
elif (side == 7):
(r, c, side) = (r - 1, c, side - 2)
if (r < 0): return (False, False)
if (c < 0): return (False, False)
# print (r,c,side)
nbr_tileno = cgra_info.rc2tileno(r, c)
# Note should return 'False' if (r,c) invalid
if DBG: print "Found nbr tile number '%s'" % str(nbr_tileno)
top_or_bottom = ''
if (cgra_info.tiletype(nbr_tileno) == "memory_tile"):
if DBG: print "HO found memory tile. is it a top or a bottom :)"
# '0' means top, '1' means bottom
top_or_bottom = str(r % 2)
if DBG:
if (top_or_bottom): print " It's a bottom"
else: print " You're the top!"
def find_neighbor(w, DBG=0):
'''E.g. find_neighbor_wire("T4_in_s1t1") => ("T5_out_s3t1")'''
# FIXME this can all be cleaned up...
if (0):
(tilefoo, wfoo) = (3, ("sb_wire_in1_s3t2", "out0_s1t2"))
(tilefoo, wfoo) = (1, ("in_s2t4"))
if (tileno == tilefoo) and (w in wfoo):
DBG = 1
print "\nWant match for tile %d wire '%s'" % (tileno, w)
# find_neighbor_wire("T4_in_s1t1") => ("T5_out_s3t1")
#
(tileno, dir, side, track) = cgra_info.parse_canon(w)
# Only works for 'out' wires (HA!)
assert dir == 'out'
in_or_out = dir
if (in_or_out == "out"): in_or_out = "in"
else: in_or_out = "out"
(r, c) = cgra_info.tileno2rc(tileno)
if DBG: print("FN: I am '%s' at (r,c) = (%d,%d)" % (w, r, c))
# top_or_bottom = parse.group(2) # 'None', '0' or '1'
top_or_bottom = side / 4 # '0' or '1'
# Adjust for wire in bottom of a memtile
if (top_or_bottom == '1'): r = r + 1
if (side == 0): (r, c, side) = (r, c + 1, side + 2)
elif (side == 1): (r, c, side) = (r + 1, c, side + 2)
elif (side == 2): (r, c, side) = (r, c - 1, side - 2)
elif (side == 3):
(r, c, side) = (r - 1, c, side - 2)
# Yes, yes, I know
elif (side == 4):
(r, c, side) = (r, c + 1, side + 2)
elif (side == 5):
(r, c, side) = (r + 1, c, side + 2)
elif (side == 6):
(r, c, side) = (r, c - 1, side - 2)
elif (side == 7):
(r, c, side) = (r - 1, c, side - 2)
if (r < 0): return (False, False)
if (c < 0): return (False, False)
# print (r,c,side)
if DBG: print("FN: My neighbor is (r,c) = (%d,%d)" % (r, c))
nbr_tileno = cgra_info.rc2tileno(r, c)
# Note should return 'False' if (r,c) invalid
if DBG: print "Found neighbor tile number '%s'" % str(nbr_tileno)
# Adjust for mem tile top/bottom
# Even row means top, odd row means bottom
if (cgra_info.tiletype(nbr_tileno) == "memory_tile"):
if DBG: print "HO found memory tile. is it a top or a bottom :)"
if (r % 2) == 0:
if DBG: print " You're the top!"
else:
if DBG: print " It's a bottom"
side = side + 4
nbr_wire = "Tx%04X_%s_s%dt%d" % (nbr_tileno, in_or_out, side, track)
# if DBG: print "%s on tile %d matches %s on tile %d\n" % (w, tileno, nbr_wire, nbr_tileno)
if DBG: print "'%s' connects to neighbor '%s'\n" % (w, nbr_wire)
return nbr_wire