def gen_hdl_areardmux(root, module, isigs, area, areas):
proc = HDLComb()
proc.name = 'AreaRdMux'
bus_addr = root.h_bus['adro']
proc.sensitivity.extend([bus_addr, isigs.MemRdData, isigs.MemRdDone])
first = []
last = first
for a in areas:
proc.sensitivity.extend([a.h_isigs.RdData, a.h_isigs.RdDone])
stmt = gen_hdl_area_decode(root, module, a, bus_addr)
stmt.then_stmts.append(HDLAssign(isigs.RdData, a.h_isigs.RdData))
stmt.then_stmts.append(HDLAssign(isigs.RdDone, a.h_isigs.RdDone))
if root.c_buserr:
proc.sensitivity.append(a.h_isigs.RdError)
stmt.then_stmts.append(HDLAssign(isigs.RdError, a.h_isigs.RdError))
if a.h_has_external:
proc.stmts.append(HDLAssign(a.h_rdsel_sig, bit_0))
stmt.then_stmts.append(HDLAssign(a.h_rdsel_sig, bit_1))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_mem2top_rd(root, module, isigs, last)
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_wrseldec(root, module, isigs, area, pfx, wrseldec):
proc = HDLComb()
proc.name = '{}WrSelDec'.format(pfx)
bus_addr = root.h_bus['adri']
proc.sensitivity.append(bus_addr)
for r in wrseldec:
for i in reversed(range(r.c_nwords)):
proc.stmts.append(HDLAssign(r.h_wrsel[i], bit_0))
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(HDLAssign(isigs.Loc_CRegWrOK, bit_0))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
for reg in wrseldec:
if reg.h_has_mux:
proc.sensitivity.append(reg.h_regok)
regok = reg.h_regok
else:
regok = bit_1
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
ch.stmts.append(HDLAssign(reg.h_wrsel[i], bit_1))
ch.stmts.append(HDLAssign(isigs.Loc_CRegWrOK, regok))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_CRegWrOK, bit_0))
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_regrdmux(root, module, isigs, area, pfx, rd_reg):
proc = HDLComb()
proc.name = '{}RegRdMux'.format(pfx)
bus_addr = root.h_bus['adro']
proc.sensitivity.append(bus_addr)
proc.sensitivity.append(isigs.CRegRdData)
proc.sensitivity.append(isigs.CRegRdOK)
for reg in rd_reg:
if reg.h_rdsel:
for i in reversed(range(reg.c_nwords)):
proc.stmts.append(HDLAssign(reg.h_rdsel[i], bit_0))
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(HDLAssign(isigs.Loc_RegRdData,
isigs.CRegRdData))
stmt.else_stmts.append(HDLAssign(isigs.Loc_RegRdOK, isigs.CRegRdOK))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
regok_sensitivity = []
for reg in rd_reg:
loc = reg.h_loc_SRFF or reg.h_loc
proc.sensitivity.append(loc)
if reg.h_has_mux:
regok_sensitivity.append(reg.h_regok)
regok = reg.h_regok
else:
regok = bit_1
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
val = loc
vwidth = reg.c_rwidth // reg.c_nwords
val = HDLSlice(val, i * root.c_word_bits, vwidth)
if vwidth < root.c_word_bits:
val = HDLZext(val, vwidth)
ch.stmts.append(HDLAssign(isigs.Loc_RegRdData, val))
ch.stmts.append(HDLAssign(isigs.Loc_RegRdOK, regok))
if reg.h_rdsel:
ch.stmts.append(HDLAssign(reg.h_rdsel[i], bit_1))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_RegRdData, isigs.CRegRdData))
ch.stmts.append(HDLAssign(isigs.Loc_RegRdOK, isigs.CRegRdOK))
proc.sensitivity.extend(regok_sensitivity)
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_memrdmux(root, module, isigs, area, pfx, mems):
proc = HDLComb()
proc.name = pfx + 'MemRdMux'
bus_addr = root.h_bus['adro']
proc.sensitivity.extend([bus_addr, isigs.RegRdData, isigs.RegRdDone])
if root.c_buserr:
proc.sensitivity.append(isigs.RegRdError)
adr_sz = ilog2(area.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
first = []
last = first
for m in mems:
data = m.children[0]
if data.access in READ_ACCESS:
proc.sensitivity.extend([m.h_rddata, m.h_rddone])
if root.c_buserr:
proc.sensitivity.append(m.h_rderror)
proc.stmts.append(HDLAssign(m.h_rdsel_sig, bit_0))
cond = HDLAnd(HDLGe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_sta),
HDLLe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_end))
stmt = HDLIfElse(cond)
if data.access in READ_ACCESS:
stmt.then_stmts.append(HDLAssign(m.h_rdsel_sig, bit_1))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdData, m.h_rddata))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdDone, m.h_rddone))
if root.c_buserr:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdError, m.h_rderror))
else:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdData, HDLReplicate(bit_0,
data.width)))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdDone, bit_0))
if root.c_buserr:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdError, root.h_bus['rd']))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_reg2locmem_rd(root, module, isigs, last)
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.extend(first)
gen_hdl_reg2locmem_rd(root, module, isigs, stmt.else_stmts)
proc.stmts.append(stmt)
else:
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_memwrmux(root, module, isigs, area, pfx, mems):
proc = HDLComb()
proc.name = pfx + 'MemWrMux'
bus_addr = root.h_bus['adri']
proc.sensitivity.extend([bus_addr, isigs.RegWrDone])
if root.c_buserr:
proc.sensitivity.append(isigs.RegWrError)
adr_sz = ilog2(area.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
first = []
last = first
for m in mems:
data = m.children[0]
set_wrsel = data.access == 'wo' or (data.access == 'rw'
and root.c_bussplit)
if set_wrsel:
proc.stmts.append(HDLAssign(m.h_wrsel_sig, bit_0))
cond = HDLAnd(HDLGe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_sta),
HDLLe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_end))
stmt = HDLIfElse(cond)
if set_wrsel:
stmt.then_stmts.append(HDLAssign(m.h_wrsel_sig, bit_1))
if data.access in WRITE_ACCESS:
proc.sensitivity.append(m.h_wrdone)
done = m.h_wrdone
else:
done = bit_0
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemWrDone, done))
if root.c_buserr:
if data.access in WRITE_ACCESS:
proc.sensitivity.append(m.h_wrerror)
err = m.h_wrerror
else:
err = root.h_bus['wr']
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemWrError, err))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_reg2locmem_wr(root, module, isigs, last)
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.extend(first)
gen_hdl_reg2locmem_wr(root, module, isigs, stmt.else_stmts)
proc.stmts.append(stmt)
else:
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_cregrdmux(root, module, isigs, area, pfx, wrseldec):
proc = HDLComb()
proc.name = '{}CRegRdMux'.format(pfx)
bus_addr = root.h_bus['adro']
proc.sensitivity.append(bus_addr)
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(
HDLAssign(isigs.Loc_CRegRdData, HDLReplicate(bit_0, None)))
stmt.else_stmts.append(HDLAssign(isigs.Loc_CRegRdOK, bit_0))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
regok_sensitivity = []
for reg in wrseldec:
if reg.h_loc:
# NOTE: not needed for WO registers!
proc.sensitivity.append(reg.h_loc)
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
if reg.access == 'wo':
val = HDLReplicate(bit_0, None)
ok = bit_0
else:
val = reg.h_loc
regw = reg.c_rwidth // reg.c_nwords
val = HDLSlice(val, i * regw, regw)
if regw < root.c_word_bits:
val = HDLZext(val, root.c_word_bits)
if reg.h_has_mux:
if i == 0:
regok_sensitivity.append(reg.h_regok)
ok = reg.h_regok
else:
ok = bit_1
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdData, val))
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdOK, ok))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdData, HDLReplicate(bit_0, None)))
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdOK, bit_0))
proc.sensitivity.extend(regok_sensitivity)
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def add_read_process(root, module, isigs):
# Register read
rd_data = root.h_bus['dato']
rd_ack = isigs.rd_ack
rd_adr = root.h_bus.get('adr', None)
rdproc = HDLComb()
if rd_adr is not None:
rdproc.sensitivity.append(rd_adr)
if root.h_max_delay >= 1:
rdproc.sensitivity.extend(
[root.h_reg_rdat_int, root.h_rd_ack1_int, isigs.rd_int])
module.stmts.append(rdproc)
# All the read are ack'ed (including the read to unassigned addresses).
rdproc.stmts.append(HDLComment("By default ack read requests"))
rdproc.stmts.append(
HDLAssign(rd_data, HDLReplicate(bit_0, root.c_word_bits)))
rdproc.stmts.append(HDLAssign(rd_ack, bit_1))
def add_read(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
s.append(HDLAssign(rd_data, root.h_reg_rdat_int))
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
s.append(HDLAssign(rd_data, n.h_bus['dato']))
rdproc.stmts.append(HDLAssign(n.h_rd, bit_0))
s.append(HDLAssign(n.h_rd, isigs.rd_int))
s.append(HDLAssign(isigs.rd_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
s.append(HDLComment("RAM {}".format(n.name)))
# TODO: handle list of registers!
r = n.children[0]
rdproc.sensitivity.append(r.h_sig_dato)
# Output ram data
s.append(HDLAssign(rd_data, r.h_sig_dato))
# Set rd signal to ram
s.append(HDLAssign(r.h_sig_rd, isigs.rd_int))
# But set it to 0 when the ram is not selected.
rdproc.stmts.append(HDLAssign(r.h_sig_rd, bit_0))
# Use delayed ack as ack.
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
return
else:
# Blocks have been handled.
raise AssertionError
stmts = []
add_decoder(root, stmts, rd_adr, root, add_read)
rdproc.stmts.extend(stmts)
def gen_hdl_areawrmux(root, module, isigs, area, areas):
proc = HDLComb()
proc.name = 'AreaWrMux'
bus_addr = root.h_bus['adri']
proc.sensitivity.extend([bus_addr, isigs.MemWrDone])
first = []
last = first
for a in areas:
proc.sensitivity.append(a.h_isigs.WrDone)
stmt = gen_hdl_area_decode(root, module, a, bus_addr)
stmt.then_stmts.append(HDLAssign(isigs.WrDone, a.h_isigs.WrDone))
if root.c_buserr:
proc.sensitivity.append(a.h_isigs.WrError)
stmt.then_stmts.append(HDLAssign(isigs.WrError, a.h_isigs.WrError))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_mem2top_wr(root, module, isigs, last)
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_reg_rdmux(reg, pfx, root, module, isigs):
proc = HDLComb()
proc.name = 'Reg_{}{}_RdMux'.format(pfx, reg.name)
sel_field = reg.h_mux.sel
proc.sensitivity.append(sel_field._parent.h_loc)
sel_val, sel_width = gen_hdl_field(sel_field._parent.h_loc, sel_field)
sw = HDLSwitch(sel_val)
proc.stmts.append(sw)
m = 0
for suff, val in reg.h_mux.codelist:
ch = HDLChoiceExpr(HDLBinConst(val, sel_width))
ch.stmts.append(HDLAssign(reg.h_loc, reg.h_loc_mux[m]))
proc.sensitivity.append(reg.h_loc_mux[m])
ch.stmts.append(HDLAssign(reg.h_regok, bit_1))
sw.choices.append(ch)
m += 1
ch = HDLChoiceDefault()
ch.stmts.append(
HDLAssign(reg.h_loc, HDLReplicate(bit_0, sel_field.c_rwidth)))
ch.stmts.append(HDLAssign(reg.h_regok, bit_0))
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_reg_wrseldec(reg, pfx, root, module, isigs):
proc = HDLComb()
proc.name = 'Reg_{}{}_WrSelDec'.format(pfx, reg.name)
sel_field = reg.h_mux.sel
proc.sensitivity.append(sel_field._parent.h_loc)
sel_val, sel_width = gen_hdl_field(sel_field._parent.h_loc, sel_field)
sw = HDLSwitch(sel_val)
for i in reversed(range(reg.c_nwords)):
proc.sensitivity.append(reg.h_wrsel[i])
for i in reversed(range(reg.c_nwords)):
for m in range(len(reg.h_mux.codelist)):
proc.stmts.append(HDLAssign(reg.h_wrsel_mux[i][m], bit_0))
m = 0
for _, val in reg.h_mux.codelist:
ch = HDLChoiceExpr(HDLBinConst(val, sel_width))
for i in reversed(range(reg.c_nwords)):
ch.stmts.append(HDLAssign(reg.h_wrsel_mux[i][m], reg.h_wrsel[i]))
m += 1
sw.choices.append(ch)
ch = HDLChoiceDefault()
sw.choices.append(ch)
proc.stmts.append(sw)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))