def test_sim(capsys): class Args(): sim = None testbench = None target = None keep = False backendargs = None setup = True build_only = False no_export = False def __init__(self, system): self.system = system from fusesoc.config import Config from fusesoc.coremanager import CoreManager build_root = os.path.join(tests_dir, 'build') config = Config() config.build_root = build_root config.cache_root = cache_root common_cm = CoreManager(config) common_cm.add_cores_root(cores_root) args = Args(system="wb_common") with pytest.raises(SystemExit): sim(common_cm, args) out, err = capsys.readouterr() assert out == "" #Workaround since this test fails with Travis on Python2.7. No idea why import sys if sys.version_info[0] > 2: assert err == "No tool was supplied on command line or found in 'wb_common' core description\n"
def system_info(args): if args.system in CoreManager().get_systems(): core = CoreManager().get_core(args.system) core.info() core.system.info() else: pr_err("Can't find system '" + args.system + "'")
def build(args): system = args.system if system in CoreManager().get_systems(): core = CoreManager().get_core(system) try: backend = BackendFactory(core) except DependencyError as e: pr_err("'" + args.system + "' or any of its dependencies requires '" + e.value + "', but this core was not found") exit(1) except RuntimeError as e: pr_err("Failed to build '{}': {}".format(args.system, e)) exit(1) try: backend.configure(args.backendargs) except RuntimeError as e: pr_err(str(e)) exit(1) print('') try: backend.build(args.backendargs) except RuntimeError as e: pr_err("Failed to build FPGA: " + str(e)) else: pr_err("Can't find system '" + args.system + "'")
def run(args): cm = CoreManager() config = Config() for cores_root in [ config.cores_root, config.systems_root, args.cores_root ]: try: cm.add_cores_root(cores_root) except (RuntimeError, IOError) as e: pr_warn("Failed to register cores root '{}'".format(str(e))) # Process global options if vars(args)['32']: config.archbits = 32 logger.debug("Forcing 32-bit mode") elif vars(args)['64']: config.archbits = 64 logger.debug("Forcing 64-bit mode") else: config.archbits = 64 if platform.architecture()[0] == '64bit' else 32 logger.debug("Autodetected " + str(config.archbits) + "-bit mode") config.monochrome = vars(args)['monochrome'] if config.monochrome: logger.debug("Monochrome output") else: logger.debug("Colorful output") config.verbose = vars(args)['verbose'] if config.verbose: logger.debug("Verbose output") else: logger.debug("Concise output") # Run the function args.func(args)
def run(args): cm = CoreManager() config = Config() for cores_root in [config.cores_root, config.systems_root, args.cores_root]: try: cm.add_cores_root(cores_root) except (RuntimeError, IOError) as e: pr_warn("Failed to register cores root '{}'".format(str(e))) # Process global options if vars(args)['32']: config.archbits = 32 logger.debug("Forcing 32-bit mode") elif vars(args)['64']: config.archbits = 64 logger.debug("Forcing 64-bit mode") else: config.archbits = 64 if platform.architecture()[0] == '64bit' else 32 logger.debug("Autodetected " + str(config.archbits) + "-bit mode") config.monochrome = vars(args)['monochrome'] if config.monochrome: logger.debug("Monochrome output") else: logger.debug("Colorful output") config.verbose = vars(args)['verbose'] if config.verbose: logger.debug("Verbose output") else: logger.debug("Concise output") # Run the function args.func(args)
def __init__(self, system, export): self.system = system self.export = export self.TOOL_NAME = self.__class__.__name__.lower() build_root = os.path.join(Config().build_root, self.system.sanitized_name) self.src_root = os.path.join(build_root, 'src') self.work_root = os.path.join(build_root, self.TOOL_TYPE + '-' + self.TOOL_NAME) self.cm = CoreManager() self.cores = self.cm.get_depends(self.system.name) self.env = os.environ.copy() #FIXME: Remove BUILD_ROOT once cores have had some time # to migrate to SRC_ROOT/WORK_ROOT self.env['BUILD_ROOT'] = os.path.abspath(build_root) self.env['SRC_ROOT'] = os.path.abspath(self.src_root) self.env['WORK_ROOT'] = os.path.abspath(self.work_root) self.plusarg = OrderedDict() self.vlogparam = OrderedDict() self.vlogdefine = OrderedDict() self.generic = OrderedDict() self.cmdlinearg = OrderedDict() self.parsed_args = False
def init_coremanager(config, args_cores_root): logger.debug("Command line arguments: " + str(sys.argv)) if os.getenv("FUSESOC_CORES"): logger.debug("FUSESOC_CORES: " + str(os.getenv("FUSESOC_CORES").split(':'))) cm = CoreManager(config) # Get the environment variable for further cores env_cores_root = [] if os.getenv("FUSESOC_CORES"): env_cores_root = os.getenv("FUSESOC_CORES").split(":") env_cores_root.reverse() core_libraries = [l['location'] for l in config.libraries.values()] for cores_root in config.cores_root + \ [config.systems_root] + \ env_cores_root + \ core_libraries + \ args_cores_root: try: cm.add_cores_root(cores_root) except (RuntimeError, IOError) as e: logger.warning("Failed to register cores root '{}'".format(str(e))) return cm
def pgm(args): if args.system in CoreManager().get_systems(): core = CoreManager().get_core(args.system) backend = BackendFactory(core) try: backend.pgm(args.backendargs) except RuntimeError as e: pr_err("Failed to program the FPGA: " + str(e)) else: pr_err("Can't find system '" + args.system + "'")
def fetch(args): core = CoreManager().get_core(args.core) if core: cores = CoreManager().get_depends(core.name) try: core.setup() except URLError as e: pr_err("Problem while fetching '" + core.name + "': " + str(e.reason)) exit(1) except HTTPError as e: pr_err("Problem while fetching '" + core.name + "': " + str(e.reason)) exit(1) for name in cores: pr_info("Fetching " + name) core = CoreManager().get_core(name) try: core.setup() except URLError as e: pr_err("Problem while fetching '" + core.name + "': " + str(e.reason)) exit(1) except HTTPError as e: pr_err("Problem while fetching '" + core.name + "': " + str(e.reason)) exit(1) else: pr_err("Can't find core '" + args.core + "'")
def sim(args): core = CoreManager().get_core(args.system) if core == None: pr_err("Can't find core '" + args.system + "'") exit(1) if args.sim: sim_name = args.sim[0] elif core.simulators: sim_name = core.simulators[0] else: pr_err("No simulator was found in '" + args.system + "' core description") logger.error("No simulator was found in '" + args.system + "' core description") exit(1) try: CoreManager().tool = sim_name sim = SimulatorFactory(sim_name, core) except DependencyError as e: pr_err("'" + args.system + "' or any of its dependencies requires '" + e.value + "', but this core was not found") exit(1) except OptionSectionMissing as e: pr_err("'" + args.system + "' miss a mandatory parameter for " + sim_name + " simulation (" + e.value + ")") exit(1) except RuntimeError as e: pr_err(str(e)) exit(1) if (args.testbench): sim.toplevel = args.testbench[0] if not args.keep or not os.path.exists(sim.sim_root): try: sim.configure(args.plusargs) print('') except RuntimeError as e: pr_err("Failed to configure the system") pr_err(str(e)) exit(1) try: sim.build() except Source as e: pr_err("'" + e.value + "' source type is not valid. Choose 'C' or 'systemC'") exit(1) except RuntimeError as e: pr_err("Failed to build simulation model") pr_err(str(e)) exit(1) if not args.build_only: try: sim.run(args.plusargs) except RuntimeError as e: pr_err("Failed to run the simulation") pr_err(str(e))
def configure(self): if os.path.exists(self.work_root): shutil.rmtree(self.work_root) os.makedirs(self.work_root) cm = CoreManager() for name in self.cores: pr_info("Preparing " + name) core = cm.get_core(name) dst_dir = os.path.join(Config().build_root, self.system.name, 'src', name) core.setup() core.export(dst_dir)
def __init__(self, system): config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.src_root = os.path.join(self.build_root, 'src') self.cm = CoreManager() self.cores = self.cm.get_depends(self.system.name) self.env = os.environ.copy() self.env['BUILD_ROOT'] = os.path.abspath(self.build_root)
def get_core(core): from fusesoc.coremanager import CoreManager from fusesoc.config import Config from fusesoc.main import _get_core config = Config() config.build_root = build_root config.cache_root = cache_root cm = CoreManager(config) cm.add_cores_root(cores_root) return _get_core(cm, core)
def test_copyto(): import os import tempfile from fusesoc.config import Config from fusesoc.coremanager import CoreManager from fusesoc.edalizer import Edalizer from fusesoc.librarymanager import Library from fusesoc.vlnv import Vlnv flags = {"tool": "icarus"} work_root = tempfile.mkdtemp(prefix="copyto_") core_dir = os.path.join(os.path.dirname(__file__), "cores", "misc", "copytocore") lib = Library("misc", core_dir) cm = CoreManager(Config()) cm.add_library(lib) core = cm.get_core(Vlnv("::copytocore")) edalizer = Edalizer( toplevel=core.name, flags=flags, core_manager=cm, cache_root=None, work_root=work_root, export_root=None, system_name=None, ) edalizer.run() eda_api = edalizer.edalize assert eda_api["files"] == [ { "file_type": "user", "core": "::copytocore:0", "logical_name": "", "name": "copied.file", "is_include_file": False, }, { "file_type": "tclSource", "core": "::copytocore:0", "logical_name": "", "name": "subdir/another.file", "is_include_file": False, }, ] assert os.path.exists(os.path.join(work_root, "copied.file")) assert os.path.exists(os.path.join(work_root, "subdir", "another.file"))
def run(args): level = logging.DEBUG if args.verbose else logging.INFO setup_logging(level=level, monchrome=args.monochrome) logger.debug("Command line arguments: " + str(sys.argv)) if os.getenv("FUSESOC_CORES"): logger.debug("FUSESOC_CORES: " + str(os.getenv("FUSESOC_CORES").split(':'))) if args.verbose: logger.debug("Verbose output") else: logger.debug("Concise output") if args.monochrome: logger.debug("Monochrome output") else: logger.debug("Colorful output") cm = CoreManager() config = Config() # Get the environment variable for further cores env_cores_root = [] if os.getenv("FUSESOC_CORES"): env_cores_root = os.getenv("FUSESOC_CORES").split(":") env_cores_root.reverse() for cores_root in [config.cores_root, config.systems_root, env_cores_root, args.cores_root]: try: cm.add_cores_root(cores_root) except (RuntimeError, IOError) as e: logger.warning("Failed to register cores root '{}'".format(str(e))) # Process global options if vars(args)['32']: config.archbits = 32 logger.debug("Forcing 32-bit mode") elif vars(args)['64']: config.archbits = 64 logger.debug("Forcing 64-bit mode") else: config.archbits = 64 if platform.architecture()[0] == '64bit' else 32 logger.debug("Autodetected " + str(config.archbits) + "-bit mode") if sys.platform == "win32": config.cygpath = vars(args)['cygpath'] if config.cygpath: logger.debug("Using cygpath translation") else: logger.debug("Using native Windows paths") # Run the function args.func(args)
def configure(self): logger.debug('configure() *Entered*') if os.path.exists(self.work_root): shutil.rmtree(self.work_root) os.makedirs(self.work_root) cm = CoreManager() for name in self.cores: print("Preparing " + name) core = cm.get_core(name) dst_dir = os.path.join(Config().build_root, self.system.name, 'src', name) core.setup() core.export(dst_dir) logger.debug('configure() -Done-')
def main(): # VUnit steals the command line args so we use an environment variable # to determine which core we're picking up toplevel = os.getenv("CORE", "") if not toplevel: sys.stderr.write("Need to provide CORE environment variable") sys.exit(1) # Create VUnit instance by parsing command line arguments vu = VUnit.from_argv() #Create singleton instances for core manager and configuration handler #Configuration manager is not needed in this example cm = CoreManager() # Assume we're running in the same directory containing the cores cm.add_cores_root(".") #Get the sorted list of dependencies starting from the top-level core try: cores = cm.get_depends(toplevel) except DependencyError as e: print("'{}' or any of its dependencies requires '{}', but this core was not found".format(top_core, e.value)) sys.exit(2) #Iterate over cores, filesets and files and add all relevant sources files to vunit incdirs = set() src_files = [] #'usage' is a list of tags to look for in the filesets. # Only look at filesets where any of these tags are present usage = ['sim'] for core_name in cores: core = cm.get_core(core_name) core.setup() basepath = core.files_root for fs in core.file_sets: if (set(fs.usage) & set(usage)) and ((core_name == toplevel) or not fs.private): for file in fs.file: if file.is_include_file: #TODO: incdirs not used right now incdirs.add(os.path.join(basepath, os.path.dirname(file.name))) else: try: vu.library(file.logical_name) except KeyError: vu.add_library(file.logical_name) vu.add_source_file(os.path.join(basepath, file.name), file.logical_name) # Run vunit function vu.main()
def init_coremanager(config, args_cores_root): logger.debug("Initializing core manager") cm = CoreManager(config) args_libs = [Library(acr, acr) for acr in args_cores_root] # Add libraries from config file, env var and command-line for library in config.libraries + args_libs: try: cm.add_library(library) except (RuntimeError, IOError) as e: _s = "Failed to register library '{}'" logger.warning(_s.format(str(e))) return cm
def _get_core(name, has_system=False): core = None try: core = CoreManager().get_core(Vlnv(name)) except RuntimeError as e: logger.error(str(e)) exit(1) except DependencyError as e: logger.error("'" + name + "' or any of its dependencies requires '" + e.value + "', but this core was not found") exit(1) if has_system and not core.get_tool({'flow': 'synth', 'tool': None}): logger.error("Unable to find synthesis info for '{}'".format(name)) exit(1) return core
def __init__(self, system): config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.src_root = os.path.join(self.build_root, 'src') if 'toplevel' in self.system.simulator: self.toplevel = self.system.simulator['toplevel'] else: self.toplevel = 'orpsoc_tb' self.vpi_modules = [] self.cm = CoreManager() self.cores = self.cm.get_depends(self.system.name) logger.debug( "depend --> " +str (self.cores)) self.env = os.environ.copy() self.env['CORE_ROOT'] = os.path.abspath(self.system.core_root) self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.env['SIMULATOR'] = self.TOOL_NAME self.verilog = _Verilog() for core_name in self.cores: logger.debug('core_name=' + core_name) core = self.cm.get_core(core_name) if core.verilog: if core.verilog.include_dirs: logger.debug('core.include_dirs=' + str(core.verilog.include_dirs)) else: logger.debug('core.include_dirs=None') self.verilog.include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilog.include_dirs] self.verilog.tb_include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilog.tb_include_dirs] self.verilog.src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.src_files] self.verilog.tb_src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.tb_src_files] if core_name == self.system.name: self.verilog.tb_src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.tb_private_src_files] if core.vpi: vpi_module = {} core_root = os.path.join(self.src_root, core_name) vpi_module['include_dirs'] = [os.path.abspath(os.path.join(core_root, d)) for d in core.vpi.include_dirs] vpi_module['src_files'] = [os.path.abspath(os.path.join(core_root, f)) for f in core.vpi.src_files] vpi_module['name'] = core.name vpi_module['libs'] = [l for l in core.vpi.libs] self.vpi_modules += [vpi_module]
def list_cores(args): cores = CoreManager().get_cores() print("\nAvailable cores:\n") if not cores: cores_root = CoreManager().get_cores_root() if cores_root: pr_err("No cores found in "+':'.join(cores_root)) else: pr_err("cores_root is not defined") exit(1) maxlen = max(map(len,cores.keys())) print('Core'.ljust(maxlen) + ' Cache status') print("="*80) for name in sorted(cores.keys()): core = cores[name] print(name.ljust(maxlen) + ' : ' + core.cache_status())
def __init__(self, system): config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.src_root = os.path.join(self.build_root, 'src') if 'toplevel' in self.system.simulator: self.toplevel = self.system.simulator['toplevel'] else: self.toplevel = 'orpsoc_tb' self.vpi_modules = [] self.cm = CoreManager() self.cores = self.cm.get_depends(self.system.name) logger.debug( "depend --> " +str (self.cores)) self.env = os.environ.copy() self.env['CORE_ROOT'] = os.path.abspath(self.system.core_root) self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.env['SIMULATOR'] = self.TOOL_NAME for core_name in self.cores: logger.debug('core_name=' + core_name) core = self.cm.get_core(core_name) if core.vpi: vpi_module = {} core_root = os.path.join(self.src_root, core_name) vpi_module['include_dirs'] = [os.path.abspath(os.path.join(core_root, d)) for d in core.vpi.include_dirs] vpi_module['src_files'] = [os.path.abspath(os.path.join(core_root, f.name)) for f in core.vpi.src_files] vpi_module['name'] = core.name vpi_module['libs'] = [l for l in core.vpi.libs] self.vpi_modules += [vpi_module]
def test_copyto(): tests_dir = os.path.dirname(__file__) core = get_core("copytocore") flags = {'tool' : 'icarus'} export_root = None work_root = os.path.join(tests_dir, 'build', core.name.sanitized_name, core.get_work_root(flags)) if os.path.exists(work_root): for f in os.listdir(work_root): if os.path.isdir(os.path.join(work_root, f)): shutil.rmtree(os.path.join(work_root, f)) else: os.remove(os.path.join(work_root, f)) else: os.makedirs(work_root) eda_api = CoreManager(Config()).setup(core.name, flags, work_root, None) assert eda_api['files'] == [{'file_type': 'user', 'logical_name': '', 'name': 'copied.file', 'is_include_file': False}, {'file_type': 'tclSource', 'logical_name': '', 'name': 'subdir/another.file', 'is_include_file': False}] assert os.path.exists(os.path.join(work_root, 'copied.file')) assert os.path.exists(os.path.join(work_root, 'subdir', 'another.file'))
def list_cores(args): cores = CoreManager().get_cores() print("\nAvailable cores:\n") if not cores: cores_root = CoreManager().get_cores_root() if cores_root: pr_err("No cores found in " + ':'.join(cores_root)) else: pr_err("cores_root is not defined") exit(1) maxlen = max(map(len, cores.keys())) print('Core'.ljust(maxlen) + ' Cache status') print("=" * 80) for name in sorted(cores.keys()): core = cores[name] print(name.ljust(maxlen) + ' : ' + core.cache_status())
def get_sim(sim, core, export=False): from fusesoc.coremanager import CoreManager from fusesoc.main import _import CoreManager().tool = sim toplevel = core.get_toplevel({}) return _import('simulator', sim)(core, export=export, toplevel=toplevel)
def configure(self): if os.path.exists(self.work_root): shutil.rmtree(self.work_root) os.makedirs(self.work_root) cm = CoreManager() for name in self.cores: pr_info("Preparing " + name) core = cm.get_core(name) dst_dir = os.path.join(Config().build_root, self.system.name, 'src', name) try: core.setup() except URLError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) except urllib.HTTPError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) core.export(dst_dir)
def test_library_add(): from fusesoc.main import add_library from fusesoc.coremanager import CoreManager tcf = tempfile.NamedTemporaryFile(mode="w+") conf = Config(file=tcf) cm = CoreManager(conf) args = Namespace() args.name = 'fusesoc-cores' args.location = None args.config = tcf args.no_auto_sync = False vars(args)['sync-uri'] = sync_uri add_library(cm, args) expected = """[library.fusesoc-cores] sync-uri = https://github.com/fusesoc/fusesoc-cores""" tcf.seek(0) result = tcf.read().strip() assert expected == result
def __init__(self, system): logger.debug('__init__() *Entered*') config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.systems_root = config.systems_root self.src_root = os.path.join(self.build_root, 'src') self.include_dirs = [] self.src_files = [] self.vhdl_src_files = [] self.cm = CoreManager() self.env = os.environ.copy() self.env['SYSTEM_ROOT'] = os.path.abspath(os.path.join(self.systems_root, self.system.name)) self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.env['BACKEND'] = self.TOOL_NAME self.cores = self.cm.get_depends(self.system.name) for core_name in self.cores: logger.debug('core_name=' + core_name) core = self.cm.get_core(core_name) if core.verilog: if core.verilog.include_dirs: logger.debug('core.include_dirs=' + str(core.verilog.include_dirs)) else: logger.debug('core.include_dirs=None') self.include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilog.include_dirs] self.src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.src_files] if core.vhdl: self.vhdl_src_files += [os.path.join(self.src_root, core_name, f) for f in core.vhdl.src_files] logger.debug('__init__() -Done-')
def test_eda_api_vpi(): import os.path import tempfile from fusesoc.config import Config from fusesoc.coremanager import CoreManager from fusesoc.vlnv import Vlnv tests_dir = os.path.dirname(__file__) build_root = tempfile.mkdtemp() cache_root = os.path.join(tests_dir, 'cache') cores_root = os.path.join(tests_dir, 'capi2_cores') work_root = os.path.join(build_root, 'work') export_root = os.path.join(build_root, 'src') config = Config() config.build_root = build_root config.cache_root = cache_root cm = CoreManager(config) cm.add_cores_root(cores_root) eda_api = cm.setup(Vlnv("vpi"), {'tool': 'icarus'}, work_root, export_root) expected = { 'files': [], 'hooks': {}, 'name': 'vpi_0', 'parameters': [], 'tool_options': { 'icarus': {} }, 'toplevel': 'not_used', 'version': '0.1.2', 'vpi': [{ 'src_files': ['../src/vpi_0/f1', '../src/vpi_0/f3'], 'include_dirs': ['../src/vpi_0/'], 'libs': ['some_lib'], 'name': 'vpi1' }, { 'src_files': ['../src/vpi_0/f4'], 'include_dirs': [], 'libs': [], 'name': 'vpi2' }] } assert eda_api == expected
def test_export(): import os import tempfile from fusesoc.config import Config from fusesoc.coremanager import CoreManager from fusesoc.edalizer import Edalizer from fusesoc.librarymanager import Library from fusesoc.vlnv import Vlnv flags = {"tool": "icarus"} build_root = tempfile.mkdtemp(prefix="export_") export_root = os.path.join(build_root, "exported_files") work_root = os.path.join(build_root, "work") core_dir = os.path.join(os.path.dirname(__file__), "cores") cm = CoreManager(Config()) cm.add_library(Library("cores", core_dir)) core = cm.get_core(Vlnv("::wb_intercon")) edalizer = Edalizer( toplevel=core.name, flags=flags, core_manager=cm, cache_root=None, work_root=work_root, export_root=export_root, system_name=None, ) edalizer.run() for f in [ "wb_intercon_1.0/dummy_icarus.v", "wb_intercon_1.0/bench/wb_mux_tb.v", "wb_intercon_1.0/bench/wb_upsizer_tb.v", "wb_intercon_1.0/bench/wb_intercon_tb.v", "wb_intercon_1.0/bench/wb_arbiter_tb.v", "wb_intercon_1.0/rtl/verilog/wb_data_resize.v", "wb_intercon_1.0/rtl/verilog/wb_mux.v", "wb_intercon_1.0/rtl/verilog/wb_arbiter.v", "wb_intercon_1.0/rtl/verilog/wb_upsizer.v", ]: assert os.path.isfile(os.path.join(export_root, f))
def __init__(self, system): config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.sanitized_name) self.src_root = os.path.join(self.build_root, 'src') self.cm = CoreManager() self.cores = self.cm.get_depends(self.system.name) self.env = os.environ.copy() self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.plusarg = {} self.vlogparam = {} self.generic = {} self.cmdlinearg = {}
def test_generators(): import os import tempfile from fusesoc.config import Config from fusesoc.coremanager import CoreManager from fusesoc.edalizer import Edalizer from fusesoc.librarymanager import Library from fusesoc.vlnv import Vlnv tests_dir = os.path.dirname(__file__) cores_dir = os.path.join(tests_dir, "capi2_cores", "misc", "generate") lib = Library("edalizer", cores_dir) cm = CoreManager(Config()) cm.add_library(lib) core = cm.get_core(Vlnv("::generate")) build_root = tempfile.mkdtemp(prefix="export_") cache_root = tempfile.mkdtemp(prefix="export_cache_") export_root = os.path.join(build_root, "exported_files") edalizer = Edalizer( toplevel=core.name, flags={"tool": "icarus"}, core_manager=cm, cache_root=cache_root, work_root=os.path.join(build_root, "work"), export_root=export_root, system_name=None, ) edalizer.run() gendir = os.path.join(cache_root, "generated", "generate-testgenerate_without_params_0") assert os.path.isfile(os.path.join(gendir, "generated.core")) assert os.path.isfile( os.path.join(gendir, "testgenerate_without_params_input.yml")) gendir = os.path.join(cache_root, "generated", "generate-testgenerate_with_params_0") assert os.path.isfile(os.path.join(gendir, "generated.core")) assert os.path.isfile( os.path.join(gendir, "testgenerate_with_params_input.yml"))
def configure(self): if os.path.exists(self.work_root): shutil.rmtree(self.work_root) os.makedirs(self.work_root) cm = CoreManager() for name in self.cores: pr_info("Preparing " + name) core = cm.get_core(name) dst_dir = os.path.join(Config().build_root, self.system.name, 'src', name) try: core.setup() except urllib.URLError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) except urllib.HTTPError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) core.export(dst_dir)
def get_sim(sim, core, export=False): import os.path from fusesoc.coremanager import CoreManager from fusesoc.config import Config from fusesoc.main import _import flags = {'flow': 'sim', 'tool': sim} eda_api = CoreManager().get_eda_api(core.name, flags) export_root = os.path.join(Config().build_root, core.name.sanitized_name, 'src') work_root = os.path.join(Config().build_root, core.name.sanitized_name, 'sim-' + sim) CoreManager().setup(core.name, flags, export=export, export_root=export_root) return _import(sim)(eda_api=eda_api, work_root=work_root)
def _get_core(name): core = None try: core = CoreManager().get_core(Vlnv(name)) except RuntimeError as e: logger.error(str(e)) exit(1) except DependencyError as e: logger.error("'" + name + "' or any of its dependencies requires '" + e.value + "', but this core was not found") exit(1) return core
def __init__(self, system): config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.system_root = system.system_root self.src_root = os.path.join(self.build_root, 'src') self.include_dirs = [] self.src_files = [] self.vhdl_src_files = [] self.cm = CoreManager() self.env = os.environ.copy() self.env['SYSTEM_ROOT'] = os.path.abspath(self.system_root) self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.env['BACKEND'] = self.TOOL_NAME self.cores = self.cm.get_depends(self.system.name) for core_name in self.cores: logger.debug('core_name=' + core_name) core = self.cm.get_core(core_name) if core.verilog: if core.verilog.include_dirs: logger.debug('core.include_dirs=' + str(core.verilog.include_dirs)) else: logger.debug('core.include_dirs=None') self.include_dirs += [ os.path.join(self.src_root, core_name, d) for d in core.verilog.include_dirs ] self.src_files += [ os.path.join(self.src_root, core_name, f) for f in core.verilog.src_files ] if core.vhdl: self.vhdl_src_files += [ os.path.join(self.src_root, core_name, f) for f in core.vhdl.src_files ]
class Backend(object): def __init__(self, system): logger.debug('__init__() *Entered*') config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.systems_root = config.systems_root self.src_root = os.path.join(self.build_root, 'src') self.include_dirs = [] self.src_files = [] self.vhdl_src_files = [] self.cm = CoreManager() self.env = os.environ.copy() self.env['SYSTEM_ROOT'] = os.path.abspath(os.path.join(self.systems_root, self.system.name)) self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.env['BACKEND'] = self.TOOL_NAME self.cores = self.cm.get_depends(self.system.name) for core_name in self.cores: logger.debug('core_name=' + core_name) core = self.cm.get_core(core_name) if core.verilog: if core.verilog.include_dirs: logger.debug('core.include_dirs=' + str(core.verilog.include_dirs)) else: logger.debug('core.include_dirs=None') self.include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilog.include_dirs] self.src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.src_files] if core.vhdl: self.vhdl_src_files += [os.path.join(self.src_root, core_name, f) for f in core.vhdl.src_files] logger.debug('__init__() -Done-') def configure(self): logger.debug('configure() *Entered*') if os.path.exists(self.work_root): shutil.rmtree(self.work_root) os.makedirs(self.work_root) cm = CoreManager() for name in self.cores: pr_info("Preparing " + name) core = cm.get_core(name) dst_dir = os.path.join(Config().build_root, self.system.name, 'src', name) core.setup() core.export(dst_dir) logger.debug('configure() -Done-') def build(self, args): for script in self.system.pre_build_scripts: script = os.path.abspath(os.path.join(self.systems_root, self.system.name, script)) pr_info("Running " + script); try: Launcher(script, cwd = os.path.abspath(self.build_root), env = self.env, shell=True).run() except RuntimeError: print("Error: script " + script + " failed") def done(self): for script in self.system.post_build_scripts: script = os.path.abspath(os.path.join(self.systems_root, self.system.name, script)) pr_info("Running " + script); try: Launcher(script, cwd = os.path.abspath(self.build_root), env = self.env, shell=True).run() except RuntimeError: print("Error: script " + script + " failed")
class Backend(object): def __init__(self, system): config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.system_root = system.system_root self.src_root = os.path.join(self.build_root, 'src') self.cm = CoreManager() self.env = os.environ.copy() self.env['SYSTEM_ROOT'] = os.path.abspath(self.system_root) self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.env['BACKEND'] = self.TOOL_NAME self.cores = self.cm.get_depends(self.system.name) def _get_fileset_files(self, usage): incdirs = set() src_files = [] for core_name in self.cores: core = self.cm.get_core(core_name) basepath = os.path.relpath(os.path.join(self.src_root, core_name), self.work_root) for fs in core.file_sets: if (set(fs.usage) & set(usage)) and ((core_name == self.system.name) or not fs.private): for file in fs.file: if file.is_include_file: incdirs.add(os.path.join(basepath, os.path.dirname(file.name))) else: file.name = os.path.join(basepath, file.name) src_files.append(file) return (src_files, incdirs) def configure(self): if os.path.exists(self.work_root): shutil.rmtree(self.work_root) os.makedirs(self.work_root) cm = CoreManager() for name in self.cores: pr_info("Preparing " + name) core = cm.get_core(name) dst_dir = os.path.join(Config().build_root, self.system.name, 'src', name) try: core.setup() except URLError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) except HTTPError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) core.export(dst_dir) self._export_backend_files() def _export_backend_files(self): src_dir = self.system.system_root dst_dir = os.path.join(self.src_root, self.system.name) export_files = self.system.backend.export() dirs = list(set(map(os.path.dirname, export_files))) for d in dirs: if not os.path.exists(os.path.join(dst_dir, d)): os.makedirs(os.path.join(dst_dir, d)) for f in export_files: if(os.path.exists(os.path.join(src_dir, f))): shutil.copyfile(os.path.join(src_dir, f), os.path.join(dst_dir, f)) else: pr_warn("File " + os.path.join(src_dir, f) + " doesn't exist") def build(self, args): for script in self.system.pre_build_scripts: script = os.path.abspath(os.path.join(self.system_root, script)) pr_info("Running " + script); try: Launcher(script, cwd = os.path.abspath(self.build_root), env = self.env, shell=True).run() except RuntimeError: print("Error: script " + script + " failed") def done(self): for script in self.system.post_build_scripts: script = os.path.abspath(os.path.join(self.system_root, script)) pr_info("Running " + script); try: Launcher(script, cwd = os.path.abspath(self.build_root), env = self.env, shell=True).run() except RuntimeError: print("Error: script " + script + " failed")
class EdaTool(object): def __init__(self, system): config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.sanitized_name) self.src_root = os.path.join(self.build_root, 'src') self.cm = CoreManager() self.cores = self.cm.get_depends(self.system.name) self.env = os.environ.copy() self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.plusarg = {} self.vlogparam = {} self.generic = {} self.cmdlinearg = {} def configure(self, args): if os.path.exists(self.work_root): for f in os.listdir(self.work_root): if os.path.isdir(os.path.join(self.work_root, f)): shutil.rmtree(os.path.join(self.work_root, f)) else: os.remove(os.path.join(self.work_root, f)) else: os.makedirs(self.work_root) for name in self.cores: pr_info("Preparing " + str(name)) core = self.cm.get_core(name) dst_dir = os.path.join(Config().build_root, self.system.sanitized_name, 'src', core.sanitized_name) try: core.setup() except URLError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) except HTTPError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) core.export(dst_dir) def parse_args(self, args, prog, paramtypes): typedict = {'bool' : {'action' : 'store_true'}, 'file' : {'type' : str , 'nargs' : 1, 'action' : FileAction}, 'int' : {'type' : int , 'nargs' : 1}, 'str' : {'type' : str , 'nargs' : 1}, } progname = 'fusesoc {} {}'.format(prog, self.system.name) parser = argparse.ArgumentParser(prog = progname, conflict_handler='resolve') param_groups = {} _descr = {'plusarg' : 'Verilog plusargs (Run-time option)', 'vlogparam' : 'Verilog parameters (Compile-time option)', 'generic' : 'VHDL generic (Run-time option)', 'cmdlinearg' : 'Command-line arguments (Run-time option)'} all_params = {} for name in self.cores: core = self.cm.get_core(name) for param_name, param in core.parameter.items(): if param.paramtype in paramtypes and \ (name == self.system.name or \ param.scope == 'public'): if not param.paramtype in param_groups: param_groups[param.paramtype] = \ parser.add_argument_group(_descr[param.paramtype]) default = None if not param.default == '': try: default = [typedict[param.datatype]['type'](param.default)] print("Converted to " + str(default[0])) except KeyError as e: pass try: param_groups[param.paramtype].add_argument('--'+param_name, help=param.description, default=default, **typedict[param.datatype]) except KeyError as e: raise RuntimeError("Invalid data type {} for parameter '{}' in '{}'".format(str(e), param_name, core.name)) all_params[param_name.replace('-','_')] = param.paramtype p = parser.parse_args(args) for key,value in vars(p).items(): paramtype = all_params[key] if value == True: getattr(self, paramtype)[key] = "true" elif value == False or value is None: pass else: if type(value[0]) == str and paramtype == 'vlogparam': _value = '"'+str(value[0])+'"' else: _value = str(value[0]) getattr(self, paramtype)[key] = _value
def core_info(args): core = CoreManager().get_core(args.core) if core: core.info() else: pr_err("Can't find core '" + args.core + "'")
class Simulator(object): def __init__(self, system): config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.src_root = os.path.join(self.build_root, 'src') if 'toplevel' in self.system.simulator: self.toplevel = self.system.simulator['toplevel'] else: self.toplevel = 'orpsoc_tb' self.vpi_modules = [] self.cm = CoreManager() self.cores = self.cm.get_depends(self.system.name) logger.debug( "depend --> " +str (self.cores)) self.env = os.environ.copy() self.env['CORE_ROOT'] = os.path.abspath(self.system.core_root) self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.env['SIMULATOR'] = self.TOOL_NAME self.verilog = _Verilog() for core_name in self.cores: logger.debug('core_name=' + core_name) core = self.cm.get_core(core_name) if core.verilog: if core.verilog.include_dirs: logger.debug('core.include_dirs=' + str(core.verilog.include_dirs)) else: logger.debug('core.include_dirs=None') self.verilog.include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilog.include_dirs] self.verilog.tb_include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilog.tb_include_dirs] self.verilog.src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.src_files] self.verilog.tb_src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.tb_src_files] if core_name == self.system.name: self.verilog.tb_src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.tb_private_src_files] if core.vpi: vpi_module = {} core_root = os.path.join(self.src_root, core_name) vpi_module['include_dirs'] = [os.path.abspath(os.path.join(core_root, d)) for d in core.vpi.include_dirs] vpi_module['src_files'] = [os.path.abspath(os.path.join(core_root, f)) for f in core.vpi.src_files] vpi_module['name'] = core.name vpi_module['libs'] = [l for l in core.vpi.libs] self.vpi_modules += [vpi_module] def configure(self): if os.path.exists(self.sim_root): for f in os.listdir(self.sim_root): if os.path.isdir(os.path.join(self.sim_root, f)): shutil.rmtree(os.path.join(self.sim_root, f)) else: os.remove(os.path.join(self.sim_root, f)) else: os.makedirs(self.sim_root) self.env['SIM_ROOT'] = os.path.abspath(self.sim_root) for name in self.cores: pr_info("Preparing " + name) dst_dir = os.path.join(Config().build_root, self.system.name, 'src', name) core = self.cm.get_core(name) try: core.setup() except URLError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) except HTTPError as e: raise RuntimeError("Problem while fetching '" + core.name + "': " + str(e.reason)) core.export(dst_dir) def build(self): for core_name in self.cores: core = self.cm.get_core(core_name) if core.scripts: run_scripts(core.scripts.pre_build_scripts, core.core_root, self.sim_root, self.env) return def run(self, args): typedict = {'bool' : {'action' : 'store_true'}, 'file' : {'type' : str , 'nargs' : 1, 'action' : FileAction}, 'int' : {'type' : int , 'nargs' : 1}, 'str' : {'type' : str , 'nargs' : 1}, } parser = argparse.ArgumentParser(prog ='fusesoc sim '+self.system.name, conflict_handler='resolve') for name in self.cores: core = self.cm.get_core(name) if core.plusargs: core.plusargs.add_arguments(parser) for param_name, param in core.parameter.items(): if name == self.system.name or param.scope == 'public': parser.add_argument('--'+param_name, help=param.description, **typedict[param.datatype]) p = parser.parse_args(args) self.plusargs = [] for key,value in vars(p).items(): if value == True: self.plusargs += [key] elif value == False or value is None: pass else: self.plusargs += [key+'='+str(value[0])] for core_name in self.cores: core = self.cm.get_core(core_name) if core.scripts: run_scripts(core.scripts.pre_run_scripts, core.core_root, self.sim_root, self.env) def done(self, args): for core_name in self.cores: core = self.cm.get_core(core_name) if core.scripts: run_scripts(core.scripts.post_run_scripts, core.core_root, self.sim_root, self.env)
class Simulator(object): def __init__(self, system): logger.debug('__init__() *Entered*') config = Config() self.system = system self.build_root = os.path.join(config.build_root, self.system.name) self.src_root = os.path.join(self.build_root, 'src') if 'toplevel' in self.system.simulator: self.toplevel = self.system.simulator['toplevel'] else: self.toplevel = 'orpsoc_tb' self.vpi_modules = [] self.cm = CoreManager() self.cores = self.cm.get_depends(self.system.name) logger.debug( "depend --> " +str (self.cores)) self.env = os.environ.copy() self.env['CORE_ROOT'] = os.path.abspath(self.system.core_root) self.env['BUILD_ROOT'] = os.path.abspath(self.build_root) self.env['SIMULATOR'] = self.TOOL_NAME self.verilog = _Verilog() for core_name in self.cores: logger.debug('core_name=' + core_name) core = self.cm.get_core(core_name) if core.verilog: if core.verilog.include_dirs: logger.debug('core.include_dirs=' + str(core.verilog.include_dirs)) else: logger.debug('core.include_dirs=None') self.verilog.include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilog.include_dirs] self.verilog.tb_include_dirs += [os.path.join(self.src_root, core_name, d) for d in core.verilog.tb_include_dirs] self.verilog.src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.src_files] self.verilog.tb_src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.tb_src_files] if core_name == self.system.name: self.verilog.tb_src_files += [os.path.join(self.src_root, core_name, f) for f in core.verilog.tb_private_src_files] if core.vpi: vpi_module = {} core_root = os.path.join(self.src_root, core_name) vpi_module['include_dirs'] = [os.path.abspath(os.path.join(core_root, d)) for d in core.vpi.include_dirs] vpi_module['src_files'] = [os.path.abspath(os.path.join(core_root, f)) for f in core.vpi.src_files] vpi_module['name'] = core.name vpi_module['libs'] = [l for l in core.vpi.libs] self.vpi_modules += [vpi_module] logger.debug('__init__() -Done-') def configure(self): logger.debug('configure() *Entered*') if os.path.exists(self.sim_root): for f in os.listdir(self.sim_root): if os.path.isdir(os.path.join(self.sim_root, f)): shutil.rmtree(os.path.join(self.sim_root, f)) else: os.remove(os.path.join(self.sim_root, f)) else: os.makedirs(self.sim_root) self.env['SIM_ROOT'] = os.path.abspath(self.sim_root) for name in self.cores: pr_info("Preparing " + name) dst_dir = os.path.join(Config().build_root, self.system.name, 'src', name) core = self.cm.get_core(name) core.setup() core.export(dst_dir) logger.debug('configure() -Done-') def build(self): return def run(self, args): logger.debug('run() *Entered*') parser = argparse.ArgumentParser(prog ='fusesoc sim '+self.system.name, conflict_handler='resolve') for name in self.cores: core = self.cm.get_core(name) if core.plusargs: core.plusargs.add_arguments(parser) p = parser.parse_args(args) self.plusargs = [] for key,value in vars(p).items(): if value == True: self.plusargs += [key] elif value == False or value is None: pass else: self.plusargs += [key+'='+str(value[0])] for script in self.system.pre_run_scripts: script = os.path.abspath(os.path.join(self.system.core_root, script)) pr_info("Running " + script); try: Launcher(script, cwd = self.sim_root, env = self.env, shell=True).run() except RuntimeError: print("Error: script " + script + " failed") def done(self, args): logger.debug('done() *Entered*') for script in self.system.post_run_scripts: script = os.path.abspath(os.path.join(self.system.core_root, script)) pr_info("Running " + script); try: Launcher(script, cwd = self.sim_root, env = self.env, shell=True).run() except RuntimeError: print("Error: script " + script + " failed")
from fusesoc.config import Config from fusesoc.coremanager import CoreManager, DependencyError from vunit import VUnitCLI, VUnit cli = VUnitCLI() cli.parser.add_argument('--core', nargs=1, required=True, help='Top-level FuseSoC core') args = cli.parse_args() # Create VUnit instance by parsing command line arguments vu = VUnit.from_args(args=args) top_core = args.core[0] #Create singleton instances for core manager and configuration handler #Configuration manager is not needed in this example cm = CoreManager() #config = Config() #Add core libraries that were picked up from fusesoc.conf by the config handler #Not really necessary for this example as we can just add 'corelib' manually try: #cm.add_cores_root(config.cores_root) cm.add_cores_root('corelib') except (RuntimeError, IOError) as e: pr_warn("Failed to register cores root '{}'".format(str(e))) #Get the sorted list of dependencies starting from the top-level core try: cores = cm.get_depends(top_core) except DependencyError as e: print("'{}' or any of its dependencies requires '{}', but this core was not found".format(top_core, e.value))