def stateMach(ind, Line): state = logs.getVar('state') if (state == 'idle'): if (Line[0] == 'addrmap') and (LINES[ind + 1][1] == 'token') and (LINES[ind + 2][1] == '{'): logs.setVar('module', LINES[ind + 1][0]) logs.setVar('state', 'work0') return ind + 3 return ind + 1 elif (state == 'work0'): if Line[0] == 'name': return skipTo(ind, ';') elif Line[0] == 'reg': next, REGLIST = getReg(ind) treatReg(REGLIST) return next elif Line[0] == '}': finalize() return len(LINES) elif Line[0] == 'eol': return ind + 1 else: print('error0', Line) return ind + 1 else: print('error1', state, Line) return ind + 1
def sequence(TestName): Seq = logs.bin2string(TestName) seq.readfile(Seq) logs.setVar('sequence', Seq) Dir = os.path.dirname(Seq) logs.setVar('testsdir', Dir) logs.log_info('SEQUENCE %d' % len(seq.Sequence))
def registerWin(Gates): Gates.sort() Was = logs.getVar('paths') if Gates not in Was: New = Was + [Gates] New.sort() logs.setVar('paths', New) print('registerWin', Gates)
def matchLevel2(Clust): Len = 0 for Key in Clust: Len += len(Clust[Key]) for Name in PATTERNS2: Items, Action = PATTERNS2[Name] if (len(Items) <= Len): logs.setVar('pattern', Name) Clust = matchDeep2(Items, Clust, Action, {}, True) return Clust
def matchCluster(Nmoses, Pmoses): # tryMatchLogicFunc(Nmoses,Pmoses) for Name in MOSPATTERNS: Npat, Ppat, Action = MOSPATTERNS[Name] if (len(Npat) == len(Nmoses)) and (len(Ppat) == len(Pmoses)): logs.setVar('pattern', Name) Match = matchDeep(Npat + Ppat, Nmoses + Pmoses, {}, True) if Match: return activate(Action, Match) logs.log_info('pattern "%s %s" was not recognized' % (Nmoses, Pmoses)) return False
def accumulate_wr(self): logs.setVar('wr_action', 0) for Slv in self.SLAVES: if self.valid(Slv + 'awvalid') and self.valid(Slv + 'awready'): self.PerfAw[Slv] += 1 if self.Firsts[Slv] == 0: self.Firsts[Slv] = logs.get_cycles() self.Lasts[Slv] = logs.get_cycles() if self.valid(Slv + 'wvalid') and self.valid(Slv + 'wready'): self.Lasts[Slv] = logs.get_cycles() self.PerfW[Slv] += 1 logs.setVar('wr_action', 1)
def tryMatchLogicFunc(Nmoses, Pmoses): Out = goodLogicCandidate(Nmoses, Pmoses) if not Out: return False print('tryMatchLogicFunc', Nmoses, Pmoses) logs.setVar('paths', []) labelDepthMos(Nmoses, 'vss', Out, [], [], []) logs.log_info('NPATHS %s' % str(logs.getVar('paths'))) NPATHS = logs.getVar('paths') logs.setVar('paths', []) labelDepthMos(Pmoses, 'vdd', Out, [], [], []) logs.log_info('PPATHS %s' % str(logs.getVar('paths'))) PPATHS = logs.getVar('paths') return NPATHS, PPATHS, Out
def treatFields(REG): if REG == []: return [] if REG[0][0] == 'field': ind, Field = getField(REG) REG1 = REG[ind:] More = treatFields(REG1) if More == []: return [Field] return [Field] + More elif REG[0][0] == 'name': logs.setVar('description', REG[2][0]) More = treatFields(REG[4:]) return More else: print('WTF %s' % REG[0]) return []
def treatReg(REGLIST): Name = REGLIST[0][0] if REGLIST[-2][0] == '}': Name2 = REGLIST[-1][0] REG2 = REGLIST[2:-2] Repeat = 1 elif REGLIST[-5][0] == '}': Name2 = REGLIST[-4][0] Repeat = eval(REGLIST[-2][0]) REG2 = REGLIST[2:-5] Fields = treatFields(REG2[:]) Desc = logs.getVar('description') logs.setVar('description', False) Obj = regClass(Name, Name2, Repeat) if Desc: Obj.description = Desc DB.append((Name, Obj)) for FF in Fields: Fh = headers(FF) if Fh != []: Fname, Access, Wid, Reset, Desc = parseField(Fh) Obj.fields.append((Fname, Access, Wid, Reset, Desc))
def main(): Fname = sys.argv[1] Path = os.path.abspath(sys.argv[0]) Path = Path.split('/') Path = '/'.join(Path[:-1]) os.system('%s/pylexer.py %s' % (Path, Fname)) readLexFile('lex.out') logs.setVar('state', 'idle') scanLexLines() Module = logs.getVar('module') Fout = open('%s.regfile' % Module, 'w') Fout.write('// translated from rdl file %s\n' % Fname) Fout.write( 'chip %s bus=apb wid=32 addrwid=16 empty=0xdeadbeef reset=async\n' % Module) for Reg, Obj in DB: if Obj.build(): if Obj.Repeat == 1: Obj.report(Fout, '') else: for XX in range(Obj.Repeat): Obj.report(Fout, '_%s' % XX) Fout.write('end\n') Fout.close()
wrds = Txt.split() if wrds[0] == 'wr': Reg = wrds[1] Flt = float(wrds[2]) Int = logs.float2binary(Flt) Str = 'tx w%s%08x' % (Reg, Int) uart = logs.getVar('uart') uart.action(Str) elif wrds[0] == 'add': Src0 = wrds[1] Src1 = wrds[2] Dst = wrds[3] Str = 'tx oadd%s%s%s' % (Src0, Src1, Dst) uart = logs.getVar('uart') uart.action(Str) elif wrds[0] == 'mul': Src0 = wrds[1] Src1 = wrds[2] Dst = wrds[3] Str = 'tx omul%s%s%s' % (Src0, Src1, Dst) uart = logs.getVar('uart') uart.action(Str) def run(self): return dr = driverClass('', logs.getVar('Monitors')) logs.setVar('dr', dr)
import veri import string, os, sys NewName = os.path.expanduser('~') sys.path.append('%s/verification_libs3' % NewName) sys.path.append('pys') import logs Monitors = [] logs.setVar('Monitors', Monitors) def initial(initfile): print('initial %s' % initfile) veri.force("rst_n", '0') if initfile != '': Queue.append('include %s' % initfile) executeCommands() execute_terminal_commands() def posedge(): return def negedge(): for Mon in Monitors: Mon.run() if veri.stime() > 5: veri.force("rst_n", '1')
#! /usr/bin/env python3 import os, sys, string from support1 import * import logs logs.setVar('PATH', (logs.__file__).replace('/logs.py', '')) #from vlexer import run_lexer from executes import execute_line import macro_verilog_pp from glvreader import glv_readfile dbx = False class EnvironmentClass: def __init__(self): self.SearchDirs = [] self.Modules = {} self.Current = None self.DontFlattens = [] self.systemverilog = False self.VerilogExtensions = ['v', 'glv', 'sv'] Env = EnvironmentClass() def main(): setupMain(Env) do_something(Env.params)