def goEspresso_external(tt, cir, exact = True):
dfile = get_project_directory()
tt_file = os.path.join(dfile, "temp", "espresso-tt.txt")
if exact:
type = '-Dexact'
else:
type = ''
write_truth_table_to_espresso(tt, cir, tt_file)
ostype = "win32"
exe = os.path.join(dfile, "utils", "bin", ostype, "espresso", "espresso.exe") + " " + type + " " + tt_file
try:
ret = subprocess.check_output(exe, shell=True).decode('UTF-8')
except:
print('ESPRESSO FAILED')
lines = ret.splitlines()
rows = lines[5 : 5 + int(lines[4][2:])]
ins = []
outs = []
for row in rows:
[i, o] = row.split(' ')
ins.append(i.replace('-','X'))
outs.append(o)
data = {i:[] for i in range(cir.outputs())}
for i in range(len(outs)):
for j in range(cir.outputs()):
if outs[i][j] == '1':
data[j].append(ins[i])
return data
def create_circuit_external_yosys (circuit):
dfile = get_project_directory()
run_path = os.path.join(dfile, "utils", "bin", "win32", "yosys")
yosys_exe = os.path.join(run_path, "yosys.exe")
circuit_file = os.path.join(dfile, "temp", "tmp_sheme_yosys.v")
run_file = os.path.join(dfile, "temp", "tmp_runfile_yosys.txt")
synth_file = os.path.join(dfile, "temp", "tmp_synth.v")
converted_circuit_file = os.path.join(dfile, "temp", "tmp_synth_conv.txt")
graph_file = os.path.join(dfile, "temp", "synth.svg")
debug_file = os.path.join(dfile, "temp", "yosys_fail.txt")
if os.path.isfile(circuit_file):
os.remove(circuit_file)
if os.path.isfile(run_file):
os.remove(run_file)
if os.path.isfile(synth_file):
os.remove(synth_file)
if os.path.isfile(converted_circuit_file):
os.remove(converted_circuit_file)
print_circuit_in_verilog_file(circuit, "circ", circuit_file)
print_run_file(run_file, circuit_file, synth_file, graph_file)
exe = yosys_exe + " < " + run_file
try:
ret = subprocess.check_output(exe, shell=True, cwd=run_path).decode('UTF-8')
except:
ret = 'Error'
if not os.path.isfile(synth_file):
# Если была проблема с Yosys выводим схему для последующего дебага
circuit.print_circuit_in_file(debug_file)
print('Yosys error')
return None
convert_file_to_relic_format(circuit, synth_file, converted_circuit_file)
if os.path.isfile(converted_circuit_file) == False:
return None
new_ckt = sa.read_scheme(converted_circuit_file)
return new_ckt
