def get_vunit_test_configs():
assert os.path.exists(VUNIT_ROOT) and len(
os.listdir(VUNIT_ROOT)) > 0, "VUnit repo not downloaded correctly"
for verilog_file in find_files(VUNIT_ROOT, "*.vhd"):
fn = get_file_name(verilog_file)
should_fail = False
lang = Language.VHDL_2008
if fn in [
"tb_deprecated",
]:
should_fail = True
defs = {}
inc_dirs = []
yield ExternTestSpec(verilog_file, lang, defs, inc_dirs, should_fail)
def get_vunit_test_configs():
check_git_submodule(VUNIT_ROOT)
for vhdl_file in find_files(VUNIT_ROOT, "*.vhd"):
fn = get_file_name(vhdl_file)
should_fail = False
lang = Language.VHDL_2008
if fn in [
"tb_deprecated",
# ? broken assert always statement?
"fifo",
]:
should_fail = True
defs = {}
inc_dirs = []
yield ExternTestSpec(vhdl_file, lang, defs, inc_dirs, should_fail)
def __new__(cls, name, bases, _dict):
def gen_test(sv_file):
def test(self):
c = HdlConvertor()
incdirs = []
c.parse([sv_file, ], Language.SYSTEM_VERILOG_2017, incdirs, debug=False)
return test
for sv_file in sv_files:
fn = get_file_name(sv_file)
test_name = "test_%s" % fn
t = gen_test(sv_file)
_dict[test_name] = t
return type.__new__(cls, name, bases, _dict)
def generate_test_method_name(self, existing_prop_dict):
fn = get_file_name(self.main_file)
return generate_test_method_name(fn, self.language, existing_prop_dict)
def get_verilator_test_configs():
check_git_submodule(VERILATOR_TEST_ROOT)
RE_TOPFILENAME = re.compile(
r'top_filename\("\s*([^"]+)"\s*\)', re.MULTILINE)
for test_script_name in find_files(VERILATOR_TEST_ROOT, "*.pl"):
do_ignore = False
for ignored in ["t_flag_", "t_dist_", "t_vlcov_",
"t_verilated_all_oldest.pl", "bootstrap.pl",
"t_driver_random.pl",
"t_debug_",
]:
if ignored in test_script_name:
do_ignore = True
break
if do_ignore:
continue
with open(test_script_name) as f:
s = f.read()
should_fail = "fails => 1" in s
main_file = RE_TOPFILENAME.search(s)
if main_file is not None:
main_file = main_file.group(1)
if "$Self->{obj_dir}" in main_file:
continue
assert main_file.startswith(
"t/") or main_file.startswith("t_"), main_file
main_file = os.path.basename(main_file)
else:
verilog_file = test_script_name.replace(".pl", ".v")
if os.path.exists(verilog_file):
main_file = os.path.basename(verilog_file)
else:
verilog_file = test_script_name.replace(".pl", ".sv")
if os.path.exists(verilog_file):
main_file = os.path.basename(verilog_file)
else:
continue
# raise NotImplementedError(test_script_name)
lang = Language.SYSTEM_VERILOG_2009
fn = get_file_name(main_file)
if os.name == 'nt':
if fn == "t_math_cond_huge":
# skip this test on windows build because appveyor runout of the memory
# and there is no free way how to increase it
continue
if fn in {
# non std {} initializer
"t_struct_init",
# should fail but fail value not parsed in script correctly
"t_var_bad_sv",
"t_mem_multi_ref_bad",
"t_langext_order",
"t_inst_missing",
# requires additional preproc definitions
"t_tri_gate",
"t_extend_class",
"t_dpi_var",
"t_dpi_sys",
"t_dpi_display",
"t_dpi_threads",
"t_interface_down_gen",
"t_gen_missing",
# "t_sys_fread",
# "t_preproc_undefineall",
# "t_lint_unused",
# "t_interface_down_gen",
# "t_case_write1",
# not a verilog files
"t_preproc_persist",
"t_preproc_noline",
"t_preproc_kwd",
"t_preproc_def09",
"t_preproc",
"t_pp_display",
"t_pp_pragmas",
"t_pipe_filter",
# non std. primitive with assign
"t_trace_primitive",
# non std. numbers starting with _
"t_stream",
# = #100'b0
"t_parse_delay",
# non std.? parameters without the parenthesis?
"t_param_no_parentheses",
# non std. ordered and named port list mixed syntax
"t_interface_modportlist",
# non std. missing return type of function
"t_interface_modport_export",
# non std. mpodport can be only in interface
"t_interface_gen",
# non std. case without items
"t_case_wild",
# /dev/null is not present under windows
"t_lint_incabspath",
# non std bind syntax
"t_func_dotted",
# `uselib
"t_mod_uselib",
# should fail but not directly noted in .pl
"t_timescale_parse_bad",
# non-std macro expansion in `timescale
"t_time_vpi",
"t_timescale_parse",
}:
should_fail = True
if fn == "t_var_rsvd":
lang = Language.SYSTEM_VERILOG_2005
preproc_defs = {
"TEST_OBJ_DIR": "obj/",
"PREDEF_COMMAND_LINE": '$display("PREDEF_COMMAND_LINE");',
"T_ASSERT_INSIDE_COND": "1",
"SIM_CYCLES": "100",
"TEST_EXPECT": "100ns",
"time_scale_units": "1fs",
"define time_scale_prec": "1fs",
}
incdirs = [VERILATOR_TEST_ROOT,
os.path.join(VERILATOR_ROOT, "include")]
yield ExternTestSpec(os.path.join(VERILATOR_TEST_ROOT, main_file),
lang, preproc_defs, incdirs, should_fail)
def get_verilog1_test_configs():
assert os.path.exists(VERILOG1_ROOT) and len(os.listdir(
VERILOG1_ROOT)) > 0, "verilog1 repo not downloaded correctly"
for verilog_file in chain(find_files(VERILOG1_ROOT, "*.v"),
find_files(VERILOG1_ROOT, "*.sv")):
fn = get_file_name(verilog_file)
should_fail = False
lang = Language.SYSTEM_VERILOG_2009
defs = {}
if fn in [
# c defined macros
"xilinx_srl",
"tff_extract",
"shregmap",
"cells_latch",
"abc_map",
"cells_latch",
"cells_map",
# not a verilog file
"xcu_cells_xtra",
"xc7_cells_xtra",
"xc6v_cells_xtra",
"xc6s_cells_xtra",
"sumprod",
"pack1",
"pack1p",
"pack2",
"pack2p",
"pack3p",
"pack3",
"opt_expr_cmp",
"map_and",
"map_xor",
"map_or",
"map_not",
"map_mux",
"map_cmp",
"flowp",
"flow",
"constmsk_testmap",
# depends on generated file
"xc7_brams_map",
"xc6s_brams_map",
"brams_map",
# (2**i)'b0
"techmap",
# error example
"syntax_err11",
"syntax_err08",
"syntax_err07",
"small",
# incorrect escaped id
"svinterface_at_top_wrapper",
# non std? +/- after specify_input_terminal_descriptor
"specify",
# non std? extra , in module port list
"opt_share_add_sub",
"opt_share_cat",
"opt_share_cat_multiuser",
"mul",
"dffs",
"memory",
# non std ID'd1
"mulshift_map",
# non std binary ~&/|
"logic",
# non std based digit starting with _
"gate2lut",
"cmp2lut",
]:
should_fail = True
if fn in ["test_dsp_model", "eagle_bb", "drams_map"]:
lang = Language.VERILOG_2005
if fn == "mux_map":
defs["MIN_MUX_INPUTS"] = "32"
if fn in ["gate2lut", "cmp2lut"]:
defs["LUT_WIDTH"] = "8"
if fn in [
"code_verilog_tutorial_fsm_full_tb",
"code_verilog_tutorial_first_counter_tb",
"code_verilog_tutorial_counter_tb",
"code_hdl_models_arbiter_tb",
]:
defs["outfile"] = "tmp/outfile"
inc_dirs = [VERILOG1_TEST_ROOT, os.path.join(VERILOG1_ROOT, "include")]
yield ExternTestSpec(verilog_file, lang, defs, inc_dirs, should_fail)
def get_yosys_test_configs():
assert os.path.exists(YOSYS_ROOT) and len(os.listdir(YOSYS_ROOT)) > 0,\
"Yosys repo not downloaded correctly (git submodule in this test directory)"
for verilog_file in chain(find_files(YOSYS_ROOT, "*.v"),
find_files(YOSYS_ROOT, "*.sv")):
fn = get_file_name(verilog_file)
should_fail = False
lang = Language.SYSTEM_VERILOG_2009
defs = {}
if fn in [
# c defined macros
"xilinx_srl",
"tff_extract",
"shregmap",
"cells_latch",
"abc_map",
"cells_latch",
"cells_map",
"cells_xtra",
# not a verilog file
"xcu_cells_xtra",
"xc7_cells_xtra",
"xc6v_cells_xtra",
"xc6s_cells_xtra",
"sumprod",
"pack1",
"pack1p",
"pack2",
"pack2p",
"pack3p",
"pack3",
"opt_expr_cmp",
"map_and",
"map_xor",
"map_or",
"map_not",
"map_mux",
"map_cmp",
"flowp",
"flow",
"constmsk_testmap",
# non std generate if syntax
"gen_if_null",
# non std var type in parenthesis
"enum_simple",
# depends on generated file
"xc2v_brams_map",
"xc7_brams_map",
"xc6s_brams_map",
"xcu_brams_map",
"brams_map",
# (2**i)'b0
"techmap",
# error example
"syntax_err11",
"syntax_err08",
"syntax_err07",
"small",
# incorrect escaped id
"svinterface_at_top_wrapper",
# non std? +/- after specify_input_terminal_descriptor
"specify",
# non std? extra , in module port list
"arith_alm_map",
"arith_map",
"bram_m10k_map",
"bram_m20k_map",
"dffs",
"lutram_mlab_map",
"mul",
"memory",
"opt_share_add_sub",
"opt_share_cat",
"opt_share_cat_multiuser",
"design",
"dsp_map",
# non std ID'd1
"mulshift_map",
# non std binary ~&/|
"logic",
# non std based digit starting with _
"gate2lut",
"cmp2lut",
# non std $ id
"abc9_map",
"abc9_unmap",
"abc9_model",
"cmp2lcu",
# non std, hierarchical name for component instance
"mul2dsp",
]:
should_fail = True
if fn in [
"test_dsp_model",
"eagle_bb",
"drams_map",
"test_dsp48a1_model",
"test_dsp48_model",
"macc_tb",
"lutrams_map",
"arith_map",
]:
lang = Language.VERILOG_2005
if fn == "mux_map":
defs["MIN_MUX_INPUTS"] = "32"
if fn in ["gate2lut", "cmp2lut"]:
defs["LUT_WIDTH"] = "8"
if fn in [
"code_verilog_tutorial_fsm_full_tb",
"code_verilog_tutorial_first_counter_tb",
"code_verilog_tutorial_counter_tb",
"code_hdl_models_arbiter_tb",
]:
defs["outfile"] = "tmp/outfile"
if fn == "quartus_rename":
defs["LCELL"] = "LCELL"
if fn in ["lut_map", "cmp2lcu", "arith_map"]:
defs["LUT_WIDTH"] = "32"
defs["LUT_SIZE"] = "64"
# if fn == "mul2dsp":
# defs["DSP_A_MAXWIDTH"] = "32"
# defs["DSP_B_MAXWIDTH"] = "64"
# defs["DSP_NAME"] = "dsp_name"
inc_dirs = []
yield ExternTestSpec(verilog_file, lang, defs, inc_dirs, should_fail)