Chips makes FPGA design quicker and easier. Chips isn't an HDL like VHDL or Verilog, its a different way of doing things. In Chips, you design components using a simple subset of the C programming language. There's a Python API to connect C components together using fast data streams to form complex, parallel systems all in a single chip. You don't need to worry about clocks, resets, or timing. You don't need to follow special templates to make your code synthesisable. All that's done for you!

$ cd test_suite
$ test_c2verilog

$ sudo python setup install

$ cd docs
$ make html

$ python setup sdist

Distribution is contained in ./dist

$ python setup bdist_wininst