__   _ __      ___  _________
          / /  (_) /____ / _ \/ ___/  _/__
         / /__/ / __/ -_) ___/ /___/ // -_)
        /____/_/\__/\__/_/   \___/___/\__/

        Copyright 2015-2016 / EnjoyDigital

     A small footprint and configurable PCIe core
      with MMAP interface and scatter-gather DMA
                powered by Migen

[> Intro
---------
LitePCIe provides a small footprint and configurable PCIe gen1/2 core.

LitePCIe is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.

Since Python is used to describe the HDL, the core is highly and easily
configurable.

LitePCIe is built using LiteX and uses technologies developed in partnership with
M-Labs Ltd:
 - Migen enables generating HDL with Python in an efficient way.
 - MiSoC provides the basic blocks to build a powerful and small footprint SoC.

LitePCIe can be used as LiteX library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.

[> Features
-----------
- 7-Series Artix7/Kintex7 PHY (up to PCIe Gen2 X2)
- Scatter-gather DMA
- Wishbone bridge
- Linux driver with DMA loopback demo and Sysfs

[> FPGA Proven
---------------
LiteEth is already used in commercial and open-source designs:
- PCIe SDR MIMO 2x2: http://www.amarisoft.com/document/SDR-MIMO-PCIe-Card.pdf


[> Possible improvements
-------------------------
- add standardized interfaces (AXI, Avalon-ST)
- add support for PCIe Gen2 X4 and X8 on 7-Series
- clean up 7-Series wrappers
- add Altera/Lattice support
- ... See below Support and consulting :)

If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list
devel [AT] lists.m-labs.hk.


[> Getting started
-------------------
1. Install Python3 and your vendor's software

2. Obtain LiteX and install it:
  git clone https://github.com/enjoy-digital/litex --recursive
  cd litex
  python3 setup.py install
  cd ..

3. Build and load PCIe DMA loopback design (only for KC705 for now):
  go to example_designs/
  run ./make.py all load-bitstream

4. Build and load Linux Driver:
  go to software/linux/kernel
  make all
  ./init.sh

5. Build and load Linux utilities:
  go to software/linux/user
  make all
  ./litepcie_util dma_loopback_test

[> Simulations
---------------
  Simulations are available in test:
    - wishbone_tb
    - dma_tb
  To run a simulation:
    go to test/
    make <simulation_name>

[> Tests
---------
  A DMA loopback example with Wishbone over Sysfs is provided.
  Please go to Getting Started section to see how to run the tests.

[> License
-----------
LitePCIe is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use LiteEth for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
 - tell us that you are using LitePCIe
 - cite LitePCIe in publications related to research it has helped
 - send us feedback and suggestions for improvements
 - send us bug reports when something goes wrong
 - send us the modifications and improvements you have done to LitePCIe.

[> Support and consulting
--------------------------
We love open-source hardware and like sharing our designs with others.

LitePCIe is mainly developed and maintained by EnjoyDigital.

If you would like to know more about LitePCIe or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.

So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)

[> Contact
E-mail: florent [AT] enjoy-digital.fr