An interactive simulation and code generation platform for Synchronous Data Flow (SDF) Graphs
SDFkit contains two parts: a design/simulation environment and code generation.
Cyclo Static Data Flow (CSDF) graphs are a popular model of computation for creating DSP applications. In the design/simulation environment, CSDF graphs can simulated and altered to optimize performance. The simulation is cycle accurate when modeling an application for an FPGA.
Actual hardware is created using code generation where the graph is translated to FPGA hardware. Since a CSDF graph is highly parallel, the parallel nature of an FPGA is exploited resulting in a high performance.
A picture is worth a thousand words:
Run pip to install requirements pip install -r requirements.txt