def put_msg(self, port_mgr, msg_addr): msg = AccessStruct(self.mem,MessageStruct,struct_addr=msg_addr) dos_pkt_addr = msg.r_s("mn_Node.ln_Name") dos_pkt = AccessStruct(self.mem,DosPacketStruct,struct_addr=dos_pkt_addr) reply_port_addr = dos_pkt.r_s("dp_Port") pkt_type = dos_pkt.r_s("dp_Type") log_file.info("DosPacket: msg=%06x -> pkt=%06x: reply_port=%06x type=%06x", msg_addr, dos_pkt_addr, reply_port_addr, pkt_type) # handle packet if pkt_type == ord('R'): # read fh_b_addr = dos_pkt.r_s("dp_Arg1") buf_ptr = dos_pkt.r_s("dp_Arg2") size = dos_pkt.r_s("dp_Arg3") # get fh and read fh = self.get_by_b_addr(fh_b_addr) data = fh.read(size) self.mem.w_block(buf_ptr, data) got = len(data) log_file.info("DosPacket: Read fh_b_addr=%06x buf=%06x len=%06x -> got=%06x fh=%s", fh_b_addr, buf_ptr, size, got, fh) dos_pkt.w_s("dp_Res1", got) elif pkt_type == ord('W'): # write fh_b_addr = dos_pkt.r_s("dp_Arg1") buf_ptr = dos_pkt.r_s("dp_Arg2") size = dos_pkt.r_s("dp_Arg3") fh = self.get_by_b_addr(fh_b_addr) data = self.mem.r_block(buf_ptr, size) fh.write(data) put = len(data) log_file.info("DosPacket: Write fh=%06x buf=%06x len=%06x -> put=%06x fh=%s", fh_b_addr, buf_ptr, size, put, fh) dos_pkt.w_s("dp_Res1", put) else: raise UnsupportedFeatureError("Unsupported DosPacket: type=%d" % pkt_type) # do reply if not port_mgr.has_port(reply_port_addr): port_mgr.register_port(reply_port_addr) port_mgr.put_msg(reply_port_addr, msg_addr)
def Remove(self, ctx): node_addr = ctx.cpu.r_reg(REG_A1) n = AccessStruct(ctx.mem, NodeStruct, node_addr) succ = n.r_s("ln_Succ") pred = n.r_s("ln_Pred") log_exec.info("Remove(%06x): ln_Pred=%06x ln_Succ=%06x" % (node_addr, pred, succ)) AccessStruct(ctx.mem, NodeStruct, pred).w_s("ln_Succ", succ) AccessStruct(ctx.mem, NodeStruct, succ).w_s("ln_Pred", pred) return node_addr
def AddHead(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) node_addr = ctx.cpu.r_reg(REG_A1) log_exec.info("AddHead(%06x, %06x)" % (list_addr, node_addr)) l = AccessStruct(ctx.mem, ListStruct, list_addr) n = AccessStruct(ctx.mem, NodeStruct, node_addr) n.w_s("ln_Pred", l.s_get_addr("lh_Head")) h = l.r_s("lh_Head") n.w_s("ln_Succ", h) AccessStruct(ctx.mem, NodeStruct, h).w_s("ln_Pred", node_addr) l.w_s("lh_Head", node_addr)
def RemTail(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) l = AccessStruct(ctx.mem, ListStruct, list_addr) node_addr = l.r_s("lh_TailPred") n = AccessStruct(ctx.mem, NodeStruct, node_addr) succ = n.r_s("ln_Succ") pred = n.r_s("ln_Pred") if pred == 0: log_exec.info("RemTail(%06x): null" % list_addr) return 0 AccessStruct(ctx.mem, NodeStruct, pred).w_s("ln_Succ", succ) AccessStruct(ctx.mem, NodeStruct, succ).w_s("ln_Pred", pred) log_exec.info("RemTail(%06x): %06x" % (list_addr, node_addr)) return node_addr
def mem_access_rw_sub_field_task_test(): mem = MockMemory() a = AccessStruct(mem, TaskStruct, 0x42) a.w_s("tc_Node.ln_Succ", 42) a.w_s("tc_Node.ln_Pred", 21) assert a.r_s("tc_Node.ln_Succ") == 42 assert a.r_s("tc_Node.ln_Pred") == 21
def StackSwap(self, ctx): stsw_ptr = ctx.cpu.r_reg(REG_A0) stsw = AccessStruct(ctx.mem, StackSwapStruct, struct_addr=stsw_ptr) # get new stack values new_lower = stsw.r_s("stk_Lower") new_upper = stsw.r_s("stk_Upper") new_pointer = stsw.r_s("stk_Pointer") # retrieve current (old) stack old_lower = self.stk_lower old_upper = self.stk_upper old_pointer = ctx.cpu.r_reg(REG_A7) # addr of sys call return # get adress of callee callee = ctx.mem.r32(old_pointer) # is a label attached to new addr if ctx.label_mgr: label = ctx.label_mgr.get_label(new_lower) if label is not None: label.name = label.name + "=Stack" # we report the old stack befor callee old_pointer += 4 log_exec.info( "StackSwap: old(lower=%06x,upper=%06x,ptr=%06x) new(lower=%06x,upper=%06x,ptr=%06x)" % (old_lower, old_upper, old_pointer, new_lower, new_upper, new_pointer)) stsw.w_s("stk_Lower", old_lower) stsw.w_s("stk_Upper", old_upper) stsw.w_s("stk_Pointer", old_pointer) self.stk_lower = new_lower self.stk_upper = new_upper # put callee's address on new stack new_pointer -= 4 ctx.mem.w32(new_pointer, callee) # activate new stack ctx.cpu.w_reg(REG_A7, new_pointer)
def AddSemaphore(self, ctx): addr = ctx.cpu.r_reg(REG_A1) sstruct = AccessStruct(ctx.mem, SignalSemaphoreStruct, addr) name_ptr = sstruct.r_s("ss_Link.ln_Name") name = ctx.mem.r_cstr(name_ptr) self.semaphore_mgr.AddSemaphore(addr, name) log_exec.info("AddSemaphore(%06x,%s)" % (addr, name))
def mem_access_invalid_node_test(): mem = MockMemory() a = AccessStruct(mem, NodeStruct, 0x42) with pytest.raises(KeyError): a.w_s("bla", 12) with pytest.raises(KeyError): a.r_s("blub")
def mem_access_bptr_test(): mem = MockMemory() a = AccessStruct(mem, MyBCPLStruct, 0x42) # write/read addr a.w_s("bs_TestBptr", 44) assert a.r_s("bs_TestBptr") == 44 # check auto converted baddr assert mem.r32(0x42) == 11
def read(self, ctx, mh_addr): self.addr = mh_addr mh = AccessStruct(ctx.mem, MemHeaderStruct, mh_addr) self.first = mh.r_s("mh_First") self.lower = mh.r_s("mh_Lower") self.upper = mh.r_s("mh_Upper") self.free = mh.r_s("mh_Free") self.total = self.upper - self.lower
def examine_file(self, fib_mem, name, sys_path): # name name_addr = fib_mem.s_get_addr('fib_FileName') # clear 32 name bytes mem = fib_mem.mem mem.clear_block(name_addr, 32, 0) mem.w_cstr(name_addr, name) # comment comment_addr = fib_mem.s_get_addr('fib_Comment') mem.w_cstr(comment_addr, "") # create the "inode" information key = self.keygen(sys_path) fib_mem.w_s('fib_DiskKey', key) log_lock.debug("examine key: %08x", key) # type if os.path.isdir(sys_path): dirEntryType = 2 else: dirEntryType = -3 fib_mem.w_s('fib_DirEntryType', dirEntryType) fib_mem.w_s('fib_EntryType', dirEntryType) # protection prot = DosProtection(0) try: os_stat = os.stat(sys_path) mode = os_stat.st_mode if mode & stat.S_IXUSR == 0: prot.clr(DosProtection.FIBF_EXECUTE) if mode & stat.S_IRUSR == 0: prot.clr(DosProtection.FIBF_READ) if mode & stat.S_IWUSR == 0: prot.clr(DosProtection.FIBF_WRITE) log_lock.debug("examine lock: '%s' mode=%03o: prot=%s", name, mode, prot) except OSError: return ERROR_OBJECT_IN_USE fib_mem.w_s('fib_Protection', prot.mask) # size if os.path.isfile(sys_path): size = os.path.getsize(sys_path) fib_mem.w_s('fib_Size', size) blocks = int((size + 511) / 512) fib_mem.w_s('fib_NumBlocks', blocks) else: fib_mem.w_s('fib_NumBlocks', 1) # date (use mtime here) date_addr = fib_mem.s_get_addr('fib_Date') date = AccessStruct(fib_mem.mem, DateStampStruct, date_addr) t = os.path.getmtime(sys_path) at = sys_to_ami_time(t) date.w_s('ds_Days', at.tday) date.w_s('ds_Minute', at.tmin) date.w_s('ds_Tick', at.tick) # fill in UID/GID fib_mem.w_s('fib_OwnerUID', 0) fib_mem.w_s('fib_OwnerGID', 0) return NO_ERROR
def mem_access_rw_field_node_test(): mem = MockMemory() a = AccessStruct(mem, NodeStruct, 0x42) a.w_s('ln_Succ', 42) a.w_s('ln_Pred', 21) a.w_s('ln_Pri', -27) assert a.r_s('ln_Succ') == 42 assert a.r_s('ln_Pred') == 21 assert a.r_s('ln_Pri') == -27
def CloseDevice(self, ctx): io_addr = ctx.cpu.r_reg(REG_A1) if io_addr != 0: io = AccessStruct(ctx.mem, IORequestStruct, io_addr) dev_addr = io.r_s("io_Device") if dev_addr != 0: log_exec.info("CloseDevice: %06x", dev_addr) self.lib_mgr.close_lib(dev_addr) io.w_s("io_Device", 0)
def volume_name_of_lock(self, lock): if lock == None: return "SYS:" else: vol_addr = lock.mem.access.r_s("fl_Volume") volnode = AccessStruct(self.mem,DosListVolumeStruct,vol_addr) name_addr = volnode.r_s("dol_Name") name = self.mem.access.r_bstr(name_addr) + ":" return name
def mem_access_rw_field_node_test(): mem = MockMemory() a = AccessStruct(mem, NodeStruct, 0x42) a.w_s("ln_Succ", 42) a.w_s("ln_Pred", 21) a.w_s("ln_Pri", -27) assert a.r_s("ln_Succ") == 42 assert a.r_s("ln_Pred") == 21 assert a.r_s("ln_Pri") == -27
def map_struct(self, name, addr, struct): size = struct.get_size() access = AccessStruct(self.mem, struct, addr) if self.label_mgr is not None: label = self.label_mgr.get_label(addr) else: label = None mem = Memory(addr, size, label, access) log_mem_alloc.info("map struct: %s", mem) return mem
def InitSemaphore(self,addr): semaphore = AccessStruct(self.mem,SignalSemaphoreStruct,struct_addr=addr) semaphore.w_s("ss_Owner",0) semaphore.w_s("ss_NestCount",0) semaphore.w_s("ss_QueueCount",0xffff) semaphore.w_s("ss_Link.ln_Type",self.NT_SIGNALSEM) semaphore.w_s("ss_WaitQueue.mlh_Head",semaphore.s_get_addr("ss_WaitQueue.mlh_Tail")) semaphore.w_s("ss_WaitQueue.mlh_Tail",0) semaphore.w_s("ss_WaitQueue.mlh_TailPred",semaphore.s_get_addr("ss_WaitQueue.mlh_Head")) return self.register_semaphore(addr)
def write_clock_data(dt, mem, data_ptr): """convert Python datetime struct to Amiga ClockData stored at pointer""" data = AccessStruct(mem, ClockDataStruct, struct_addr=data_ptr) # fill in date struct data.w_s('sec', dt.second) data.w_s('min', dt.minute) data.w_s('hour', dt.hour) data.w_s('mday', dt.day) data.w_s('month', dt.month) data.w_s('year', dt.year) data.w_s('wday', dt.weekday())
def write_clock_data(dt, mem, data_ptr): """convert Python datetime struct to Amiga ClockData stored at pointer""" data = AccessStruct(mem, ClockDataStruct, struct_addr=data_ptr) # fill in date struct data.w_s("sec", dt.second) data.w_s("min", dt.minute) data.w_s("hour", dt.hour) data.w_s("mday", dt.day) data.w_s("month", dt.month) data.w_s("year", dt.year) data.w_s("wday", dt.weekday())
def ReadEClock(self, ctx): eclockval = ctx.cpu.r_reg(REG_A0) dt = datetime.now() # abuse DateStampStruct tv = AccessStruct(ctx.mem, DateStampStruct, struct_addr=eclockval) tv.ds_Days = dt.microsecond / 1000000 tv.ds_Minute = dt.microsecond % 1000000 return 50
def map_struct(self, addr, struct, label=None): size = struct.get_size() access = AccessStruct(self.mem, struct, addr) if label and self.label_mgr: label_obj = LabelStruct(label, addr, struct) self.label_mgr.add_label(label_obj) else: label_obj = None mem = Memory(addr, size, label_obj, access) log_mem_alloc.info("map struct: %s", mem) return mem
def console_put_msg(self, port_mgr, msg_addr): msg = AccessStruct(self.mem, MessageStruct, struct_addr=msg_addr) dos_pkt_addr = msg.r_s("mn_Node.ln_Name") dos_pkt = AccessStruct(self.mem, DosPacketStruct, struct_addr=dos_pkt_addr) reply_port_addr = dos_pkt.r_s("dp_Port") pkt_type = dos_pkt.r_s("dp_Type") log_file.info( "Console DosPacket: msg=%06x -> pkt=%06x: reply_port=%06x type=%06x", msg_addr, dos_pkt_addr, reply_port_addr, pkt_type, ) # fake result dos_pkt.w_s("dp_Res1", 0) # do reply if not port_mgr.has_port(reply_port_addr): port_mgr.register_port(reply_port_addr) port_mgr.put_msg(reply_port_addr, msg_addr)
def _release_locklist(self, entry): alist_addr = entry.access.r_s("dol_List") entry.access.w_s("dol_List",0) entry.alist = [] while alist_addr != 0: alist = AccessStruct(self.mem,AssignListStruct,alist_addr) oldlock_addr = alist.r_s("al_Lock") oldlock = self.lock_mgr.get_by_b_addr(oldlock_addr >> 2) self.lock_mgr.release_lock(oldlock) entry.alist.remove(alist) nextaddr = alist.access.r_s("al_Next") self.alloc.free_struct(alist.mem) alist_addr = nextaddr
def _fill_fib(self, ctx, path): # fill FileInfo of first match in anchor lock = self.lock_mgr.create_lock(self.lock, path, False) if lock == None: return ERROR_OBJECT_NOT_FOUND fib_ptr = self.anchor.s_get_addr('ap_Info') fib = AccessStruct(ctx.mem, FileInfoBlockStruct, struct_addr=fib_ptr) io_err = lock.examine_lock(fib) self.lock_mgr.release_lock(lock) # store path name of first name at end of structure if self.str_len > 0: path_ptr = self.anchor.s_get_addr('ap_Buf') self.anchor.w_cstr(path_ptr, path) return io_err
def alloc_struct(self, name, struct, size=None, add_label=True): if size is None: size = struct.get_size() addr = self.alloc_mem(size) if self.label_mgr is not None and add_label: label = LabelStruct(name, addr, struct) self.label_mgr.add_label(label) else: label = None access = AccessStruct(self.mem, struct, addr) mem = Memory(addr, size, label, access) log_mem_alloc.info("alloc struct: %s", mem) self.mem_objs[addr] = mem return mem
def alloc_struct(self, struct, size=None, label=None): if size is None: size = struct.get_size() addr = self.alloc_mem(size) if label and self.label_mgr: label_obj = LabelStruct(label, addr, struct) self.label_mgr.add_label(label_obj) else: label_obj = None access = AccessStruct(self.mem, struct, addr) mem = Memory(addr, size, label_obj, access) log_mem_alloc.info("alloc struct: %s", mem) self.mem_objs[addr] = mem return mem
def _add_entry(self, entry): # allocate amiga entry entry.locks = [] entry.alist = [] entry.mem = self.alloc.alloc_struct(entry.name,entry.struct_def) entry.baddr = entry.mem.addr >> 2 entry.access = AccessStruct(self.mem,entry.struct_def,entry.mem.addr) entry.name_addr = self.alloc.alloc_bstr("DosListName",entry.name) entry.access.w_s("dol_Name",entry.name_addr.addr) # register in lists self.entries_by_b_addr[entry.baddr] = entry self.entries_by_name[entry.name.lower()] = entry self.entries.append(entry) log_doslist.info("add entry: %s", entry)
def get_by_b_addr(self, b_addr, none_if_missing=False): if b_addr == 0: return None else: raw_lock = AccessStruct(self.mem, FileLockStruct, b_addr << 2) key = raw_lock.r_s("fl_Key") lock_key = self.keys[key] log_lock.debug( "lookup key in baddr=%08x: %s -> lock_key=%r", b_addr, key, lock_key ) lock = lock_key.find_lock_by_baddr(b_addr) if lock: return lock else: raise VamosInternalError("lock not found by b_addr?!")
def OpenDevice(self, ctx): name_ptr = ctx.cpu.r_reg(REG_A0) unit = ctx.cpu.r_reg(REG_D0) io_addr = ctx.cpu.r_reg(REG_A1) io = AccessStruct(ctx.mem, IORequestStruct, io_addr) flags = ctx.cpu.r_reg(REG_D1) name = ctx.mem.r_cstr(name_ptr) addr = self.lib_mgr.open_lib(name) io.w_s("io_Device", addr) if addr == 0: log_exec.info("OpenDevice: '%s' unit %d flags %d -> NULL", name, unit, flags) return -1 else: log_exec.info("OpenDevice: '%s' unit %d flags %d -> %06x", name, unit, flags, addr) return 0
def alloc_lib(self, lib_struct, pos_size=0, neg_size=0, fd=None, label=None): if pos_size == 0: pos_size = lib_struct.get_size() # round neg_size to multiple of four neg_size = (neg_size + 3) & ~3 size = neg_size + pos_size # alloc full size addr = self.alloc_mem(size) base_addr = addr + neg_size if label and self.label_mgr: label_obj = LabelLib(label, base_addr, neg_size, pos_size, lib_struct, fd) self.label_mgr.add_label(label_obj) else: label_obj = None access = AccessStruct(self.mem, lib_struct, base_addr) mem = Memory(addr, size, label_obj, access) log_mem_alloc.info("alloc lib: %s", mem) self.mem_objs[addr] = mem return mem