def add_rtio(self, rtio_channels): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtio0 = rx0(DRTIOSatellite( self.drtio_transceiver.channels[0], rtio_channels, self.rx_synchronizer)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"])
def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, ethmac_nrxslots=4, ethmac_ntxslots=4, **kwargs) add_identifier(self, suffix=identifier_suffix, gateware_identifier_str=gateware_identifier_str) self.rtio_clk_freq = rtio_clk_freq platform = self.platform if with_wrpll: clock_recout_pads = platform.request("ddmtd_rec_clk") else: clock_recout_pads = None if with_sfp: # Use SFP0 to connect to master (Kasli) self.comb += platform.request("sfp_tx_disable", 0).eq(0) drtio_uplink = platform.request("sfp", 0) else: drtio_uplink = platform.request("fat_pipe", 0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("cdr_clk_clean"), data_pads=[drtio_uplink, platform.request("rtm_amc_link")], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq, clock_recout_pads=clock_recout_pads) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] self.drtio_cri = [] for i in range(len(self.drtio_transceiver.channels)): coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtioaux_csr_group.append(coreaux_name) drtioaux_memory_group.append(memory_name) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) if i == 0: self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr(DRTIOSatellite( self.rtio_tsc, self.drtio_transceiver.channels[i], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") else: corerep_name = "drtiorep" + str(i-1) drtiorep_csr_group.append(corerep_name) core = cdr(DRTIORepeater( self.rtio_tsc, self.drtio_transceiver.channels[i])) setattr(self.submodules, corerep_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) coreaux = cdr(DRTIOAuxController(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800*i self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) rtio_clk_period = 1e9/rtio_clk_freq self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) if with_wrpll: self.comb += [ platform.request("filtered_clk_sel").eq(0), platform.request("ddmtd_main_dcxo_oe").eq(1), platform.request("ddmtd_helper_dcxo_oe").eq(1) ] self.submodules.wrpll_sampler = DDMTDSamplerExtFF( platform.request("ddmtd_inputs")) self.submodules.wrpll = WRPLL( helper_clk_pads=platform.request("ddmtd_helper_clk"), main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"), helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"), ddmtd_inputs=self.wrpll_sampler) self.csr_devices.append("wrpll") platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk) else: self.comb += platform.request("filtered_clk_sel").eq(1) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, ultrascale=True, rtio_clk_freq=rtio_clk_freq) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk)
def __init__(self, rtio_clk_freq=150e6, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128*1024, **kwargs) add_identifier(self) platform = self.platform disable_si5324_ibuf = Signal(reset=1) disable_si5324_ibuf.attr.add("no_retiming") si5324_clkout = platform.request("si5324_clkout") si5324_clkout_buf = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=disable_si5324_ibuf, i_I=si5324_clkout.p, i_IB=si5324_clkout.n, o_O=si5324_clkout_buf) qpll_drtio_settings = QPLLSettings( refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings) self.submodules += qpll sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)] self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls] self.submodules.drtio_transceiver = gtp_7series.GTP( qpll_channel=qpll.channels[0], data_pads=[platform.request("sfp", i) for i in range(3)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.sync += disable_si5324_ibuf.eq( ~self.drtio_transceiver.stable_clkin.storage) self.comb += [sfp_ctl.led.eq(channel.rx_ready) for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)] self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] self.drtio_cri = [] for i in range(3): coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtioaux_csr_group.append(coreaux_name) drtioaux_memory_group.append(memory_name) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) if i == 0: self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr(DRTIOSatellite( self.rtio_tsc, self.drtio_transceiver.channels[i], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") else: corerep_name = "drtiorep" + str(i-1) drtiorep_csr_group.append(corerep_name) core = cdr(DRTIORepeater( self.rtio_tsc, self.drtio_transceiver.channels[i])) setattr(self.submodules, corerep_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) coreaux = cdr(DRTIOAuxController(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800*i self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, ref_clk=self.crg.clk125_div2, ref_div2=True, rtio_clk_freq=rtio_clk_freq) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None rtio_clk_period = 1e9/rtio_clk_freq gtp = self.drtio_transceiver.gtps[0] platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk) for gtp in self.drtio_transceiver.gtps[1:]: platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.rxoutclk) self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(platform)
def __init__(self, with_sawg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ident=artiq_version, **kwargs) if with_sawg: warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.") platform = self.platform rtio_clk_freq = 150e6 self.submodules += Microscope(platform.request("serial", 1), self.clk_freq) self.submodules.rtio_clkmul = _RTIOClockMultiplier( platform, rtio_clk_freq) rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_simple.Output(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_simple.InOut(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("si5324_clkout"), data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtio0 = rx0( DRTIOSatellite(self.drtio_transceiver.channels[0], rtio_channels, self.rx_synchronizer)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), si5324_clkout_fabric=platform.request("si5324_clkout_fabric")) platform.add_platform_command( "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]", mmcm_ps=self.siphaser.mmcm_ps_output) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None rtio_clk_period = 1e9 / rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk)
def __init__(self, rtio_clk_freq, *, with_wrpll, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", **kwargs) add_identifier(self) self.rtio_clk_freq = rtio_clk_freq platform = self.platform disable_cdrclkc_ibuf = Signal(reset=1) disable_cdrclkc_ibuf.attr.add("no_retiming") cdrclkc_clkout = platform.request("cdr_clk_clean") cdrclkc_clkout_buf = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=disable_cdrclkc_ibuf, i_I=cdrclkc_clkout.p, i_IB=cdrclkc_clkout.n, o_O=cdrclkc_clkout_buf) qpll_drtio_settings = QPLLSettings( refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) qpll = QPLL(cdrclkc_clkout_buf, qpll_drtio_settings) self.submodules += qpll self.submodules.drtio_transceiver = gtp_7series.GTP( qpll_channel=qpll.channels[0], data_pads=[platform.request("rtm_amc_link", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.sync += disable_cdrclkc_ibuf.eq( ~self.drtio_transceiver.stable_clkin.storage) self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr(DRTIOSatellite( self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") coreaux = cdr(DRTIOAuxController(core.link_layer)) self.submodules.drtioaux0 = coreaux self.csr_devices.append("drtioaux0") memory_address = self.mem_map["drtioaux"] self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtioaux", ["drtioaux0"]) self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"]) gtp = self.drtio_transceiver.gtps[0] rtio_clk_period = 1e9/rtio_clk_freq self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) if with_wrpll: self.comb += [ platform.request("filtered_clk_sel").eq(0), platform.request("ddmtd_main_dcxo_oe").eq(1), platform.request("ddmtd_helper_dcxo_oe").eq(1) ] self.submodules.wrpll_sampler = DDMTDSamplerGTP( self.drtio_transceiver, platform.request("cdr_clk_clean_fabric")) self.submodules.wrpll = WRPLL( helper_clk_pads=platform.request("ddmtd_helper_clk"), main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"), helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"), ddmtd_inputs=self.wrpll_sampler) self.csr_devices.append("wrpll") platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk) platform.add_false_path_constraints(self.wrpll.cd_helper.clk, gtp.rxoutclk) else: self.comb += platform.request("filtered_clk_sel").eq(1) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, ref_clk=self.crg.cd_sys.clk, ref_div2=True, rtio_clk_freq=rtio_clk_freq) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk) self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(platform)
def __init__(self, with_sawg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, **kwargs) RTMCommon.__init__(self) add_identifier(self, suffix=".without-sawg" if not with_sawg else "") self.config["HMC830_REF"] = "150" platform = self.platform rtio_clk_freq = 150e6 rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_serdes_ultrascale.Output(4, sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_serdes_ultrascale.InOut(4, sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG( platform, use_rtio_clock=True) if with_sawg: cls = AD9154 else: cls = AD9154NoSAWG self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0) self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1) self.csr_devices.append("ad9154_crg") self.csr_devices.append("ad9154_0") self.csr_devices.append("ad9154_1") self.config["HAS_AD9154"] = None self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"]) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend( rtio.Channel.from_phy(phy) for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs for phy in sawg.phys) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") drtio_data_pads = [platform.request("sfp", 0)] if self.hw_rev == "v2.0": drtio_data_pads.append(platform.request("rtm_amc_link")) self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("cdr_clk_clean"), data_pads=drtio_data_pads, sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtiosat = rx0( DRTIOSatellite(self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) self.csr_devices.append("drtiosat") self.submodules.drtioaux0 = rx0( DRTIOAuxController(self.drtiosat.link_layer)) self.csr_devices.append("drtioaux0") self.add_wb_slave(self.mem_map["drtioaux"], 0x800, self.drtioaux0.bus) self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtioaux", ["drtioaux0"]) self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"]) self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) self.comb += [ self.drtiosat.cri.connect(self.local_io.cri), self.drtiosat.async_errors.eq(self.local_io.async_errors), ] self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, ultrascale=True, rtio_clk_freq=rtio_clk_freq) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( platform.request("dac_sysref"), self.rtio_tsc.coarse_ts) self.csr_devices.append("sysref_sampler") self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref) self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref) rtio_clk_period = 1e9 / rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period / 2) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk) # placeholder code to test I/O routing and standards if self.hw_rev == "v2.0": self.clock_domains.cd_ddmtd_helper = ClockDomain(reset_less=True) helper_clk = platform.request("ddmtd_helper_clk") self.specials += Instance("IBUFGDS", i_I=helper_clk.p, i_IB=helper_clk.n, o_O=self.cd_ddmtd_helper.clk) ddmtd = platform.request("ddmtd_results") self.sync.ddmtd_helper += platform.request("tp16").eq( ddmtd.rec_clk ^ ddmtd.main_xo)
def __init__(self, rtio_clk_freq=150e6, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", **kwargs) add_identifier(self) platform = self.platform disable_si5324_ibuf = Signal(reset=1) disable_si5324_ibuf.attr.add("no_retiming") si5324_clkout = platform.request("cdr_clk_clean") si5324_clkout_buf = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=disable_si5324_ibuf, i_I=si5324_clkout.p, i_IB=si5324_clkout.n, o_O=si5324_clkout_buf) qpll_drtio_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings) self.submodules += qpll if self.hw_rev == "v1.0": drtio_data_pads = platform.request("sata", 0) elif self.hw_rev == "v2.0": drtio_data_pads = platform.request("rtm_amc_link", 0) else: raise NotImplementedError self.submodules.drtio_transceiver = gtp_7series.GTP( qpll_channel=qpll.channels[0], data_pads=[drtio_data_pads], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.sync += disable_si5324_ibuf.eq( ~self.drtio_transceiver.stable_clkin.storage) self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr( DRTIOSatellite(self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") coreaux = cdr(DRTIOAuxController(core.link_layer)) self.submodules.drtioaux0 = coreaux self.csr_devices.append("drtioaux0") memory_address = self.mem_map["drtioaux"] self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtioaux", ["drtioaux0"]) self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, ref_clk=self.crg.cd_sys.clk, ref_div2=True, rtio_clk_freq=rtio_clk_freq) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None rtio_clk_period = 1e9 / rtio_clk_freq gtp = self.drtio_transceiver.gtps[0] platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk) self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(platform)
def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, **kwargs) add_identifier(self, gateware_identifier_str=gateware_identifier_str) if isinstance(self.platform.toolchain, XilinxVivadoToolchain): self.platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", ]) if isinstance(self.platform.toolchain, XilinxISEToolchain): self.platform.toolchain.bitgen_opt += " -g compress" platform = self.platform self.comb += platform.request("sfp_tx_disable_n").eq(1) tx_pads = [ platform.request("sfp_tx"), platform.request("user_sma_mgt_tx") ] rx_pads = [ platform.request("sfp_rx"), platform.request("user_sma_mgt_rx") ] if sma_as_sat: tx_pads = tx_pads[::-1] rx_pads = rx_pads[::-1] # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), tx_pads=tx_pads, rx_pads=rx_pads, sys_clk_freq=self.clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] self.drtio_cri = [] for i in range(len(self.drtio_transceiver.channels)): coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtioaux_csr_group.append(coreaux_name) drtioaux_memory_group.append(memory_name) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) # Satellite if i == 0: self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr(DRTIOSatellite( self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") # Repeaters else: corerep_name = "drtiorep" + str(i-1) drtiorep_csr_group.append(corerep_name) core = cdr(DRTIORepeater( self.rtio_tsc, self.drtio_transceiver.channels[i])) setattr(self.submodules, corerep_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) coreaux = cdr(DRTIOAuxController(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800*i self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) # Si5324 Phaser self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, ultrascale=False, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")), platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) ] rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) gtx0 = self.drtio_transceiver.gtxs[0] platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtx0.txoutclk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel # (Each channel performs single-lane phase alignment for RX) for gtx in self.drtio_transceiver.gtxs[1:]: platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtx.rxoutclk) rtio_channels = [] for i in range(8): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for sma in "user_sma_gpio_p", "user_sma_gpio_n": phy = ttl_simple.InOut(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors) self.submodules.cri_con = rtio.CRIInterconnectShared( [self.drtiosat.cri], [self.local_io.cri] + self.drtio_cri, mode="sync", enable_routing=True) self.csr_devices.append("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table")
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs): BaseSoC.__init__(self, cpu_type="vexriscv", sdram_controller_type="minicon", l2_size=128 * 1024, **kwargs) add_identifier(self, gateware_identifier_str=gateware_identifier_str) platform = self.platform disable_cdr_clk_ibuf = Signal(reset=1) disable_cdr_clk_ibuf.attr.add("no_retiming") if self.platform.hw_rev == "v2.0": cdr_clk_clean = self.platform.request("cdr_clk_clean") else: cdr_clk_clean = self.platform.request("si5324_clkout") cdr_clk_clean_buf = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=disable_cdr_clk_ibuf, i_I=cdr_clk_clean.p, i_IB=cdr_clk_clean.n, o_O=cdr_clk_clean_buf) qpll_drtio_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) qpll = QPLL(cdr_clk_clean_buf, qpll_drtio_settings) self.submodules += qpll drtio_data_pads = [] if enable_sata: drtio_data_pads.append(platform.request("sata")) drtio_data_pads += [platform.request("sfp", i) for i in range(3)] if self.platform.hw_rev == "v2.0": drtio_data_pads.append(platform.request("sfp", 3)) if self.platform.hw_rev in ("v1.0", "v1.1"): sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)] self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls] self.submodules.drtio_transceiver = gtp_7series.GTP( qpll_channel=qpll.channels[0], data_pads=drtio_data_pads, sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.sync += disable_cdr_clk_ibuf.eq( ~self.drtio_transceiver.stable_clkin.storage) if enable_sata: sfp_channels = self.drtio_transceiver.channels[1:] else: sfp_channels = self.drtio_transceiver.channels if self.platform.hw_rev in ("v1.0", "v1.1"): self.comb += [ sfp_ctl.led.eq(channel.rx_ready) for sfp_ctl, channel in zip(sfp_ctls, sfp_channels) ] if self.platform.hw_rev == "v2.0": self.comb += [ self.virtual_leds.get(i).eq(channel.rx_ready) for i, channel in enumerate(sfp_channels) ] self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] self.drtio_cri = [] for i in range(len(self.drtio_transceiver.channels)): coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtioaux_csr_group.append(coreaux_name) drtioaux_memory_group.append(memory_name) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) if i == 0: self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr( DRTIOSatellite(self.rtio_tsc, self.drtio_transceiver.channels[i], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") else: corerep_name = "drtiorep" + str(i - 1) drtiorep_csr_group.append(corerep_name) core = cdr( DRTIORepeater(self.rtio_tsc, self.drtio_transceiver.channels[i])) setattr(self.submodules, corerep_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) coreaux = cdr(DRTIOAuxController(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800 * i self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 rtio_clk_period = 1e9 / rtio_clk_freq self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) if with_wrpll: self.submodules.wrpll_sampler = DDMTDSamplerGTP( self.drtio_transceiver, platform.request("cdr_clk_clean_fabric")) helper_clk_pads = platform.request("ddmtd_helper_clk") self.submodules.wrpll = WRPLL( helper_clk_pads=helper_clk_pads, main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"), helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"), ddmtd_inputs=self.wrpll_sampler) self.csr_devices.append("wrpll") # note: do not use self.wrpll.cd_helper.clk; otherwise, vivado craps out with: # critical warning: create_clock attempting to set clock on an unknown port/pin # command: "create_clock -period 7.920000 -waveform {0.000000 3.960000} -name # helper_clk [get_xlnx_outside_genome_inst_pin 20 0] platform.add_period_constraint(helper_clk_pads.p, rtio_clk_period * 0.99) platform.add_false_path_constraints(self.crg.cd_sys.clk, helper_clk_pads.p) else: self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("cdr_clk") if platform.hw_rev == "v2.0" else platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, ref_clk=self.crg.clk125_div2, ref_div2=True, rtio_clk_freq=rtio_clk_freq) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None gtp = self.drtio_transceiver.gtps[0] platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk) if with_wrpll: platform.add_false_path_constraints(helper_clk_pads.p, gtp.rxoutclk) for gtp in self.drtio_transceiver.gtps[1:]: platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.rxoutclk) self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(platform)
def __init__(self, with_sawg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128*1024, **kwargs) RTMCommon.__init__(self) add_identifier(self, suffix=".without-sawg" if not with_sawg else "") self.config["HMC830_REF"] = "150" platform = self.platform rtio_clk_freq = 150e6 rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_simple.Output(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_simple.InOut(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG( platform, use_rtio_clock=True) if with_sawg: cls = AD9154 else: cls = AD9154NoSAWG self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0) self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1) self.csr_devices.append("ad9154_crg") self.csr_devices.append("ad9154_0") self.csr_devices.append("ad9154_1") self.config["HAS_AD9154"] = None self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"]) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend(rtio.Channel.from_phy(phy) for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs for phy in sawg.phys) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("si5324_clkout"), data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtiosat = rx0(DRTIOSatellite( self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) self.csr_devices.append("drtiosat") self.submodules.drtioaux0 = rx0(DRTIOAuxController( self.drtiosat.link_layer)) self.csr_devices.append("drtioaux0") self.add_wb_slave(self.mem_map["drtioaux"], 0x800, self.drtioaux0.bus) self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtioaux", ["drtioaux0"]) self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"]) self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) self.comb += [ self.drtiosat.cri.connect(self.local_io.cri), self.drtiosat.async_errors.eq(self.local_io.async_errors), ] self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), si5324_clkout_fabric=platform.request("si5324_clkout_fabric")) platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]", mmcm_ps=self.siphaser.mmcm_ps_output) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( self.rtio_tsc.coarse_ts, self.ad9154_crg.jref) self.csr_devices.append("sysref_sampler") rtio_clk_period = 1e9/rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk)
def __init__(self, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ident=artiq_version, **kwargs) platform = self.platform rtio_clk_freq = 150e6 rtio_channels = [] phy = ttl_simple.Output(platform.request("user_led", 0)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(1, 3): phy = ttl_simple.Output(platform.request("sfp_ctl", i).led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") disable_si5324_ibuf = Signal(reset=1) disable_si5324_ibuf.attr.add("no_retiming") si5324_clkout = platform.request("si5324_clkout") si5324_clkout_buf = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=disable_si5324_ibuf, i_I=si5324_clkout.p, i_IB=si5324_clkout.n, o_O=si5324_clkout_buf) qpll_drtio_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings) self.submodules += qpll self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0) self.submodules.drtio_transceiver = gtp_7series.GTP( qpll_channel=qpll.channels[0], data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.sync += disable_si5324_ibuf.eq( ~self.drtio_transceiver.stable_clkin.storage) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtio0 = rx0( DRTIOSatellite(self.drtio_transceiver.channels[0], rtio_channels, self.rx_synchronizer)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) si5324_clkin = platform.request("si5324_clkin") self.specials += \ Instance("OBUFDS", i_I=ClockSignal("rtio_rx0"), o_O=si5324_clkin.p, o_OB=si5324_clkin.n ) i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None rtio_clk_period = 1e9 / rtio_clk_freq gtp = self.drtio_transceiver.gtps[0] platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk)
def __init__(self, gateware_identifier_str=None, sma_as_sat=False, drtio_100mhz=False, **kwargs): BaseSoC.__init__(self, cpu_type="vexriscv", cpu_bus_width=64, sdram_controller_type="minicon", l2_size=128 * 1024, integrated_sram_size=8192, **kwargs) add_identifier(self, gateware_identifier_str=gateware_identifier_str) if isinstance(self.platform.toolchain, XilinxVivadoToolchain): self.platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", ]) if isinstance(self.platform.toolchain, XilinxISEToolchain): self.platform.toolchain.bitgen_opt += " -g compress" platform = self.platform platform.add_extension(_reprogrammed3v3_io) platform.add_extension(_ams101_dac) self.comb += platform.request("sfp_tx_disable_n_33").eq(1) data_pads = [platform.request("sfp"), platform.request("user_sma_mgt")] if sma_as_sat: data_pads = data_pads[::-1] rtio_clk_freq = 100e6 if drtio_100mhz else 125e6 # 1000BASE_BX10 Ethernet compatible, 100/125MHz RTIO clock self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] self.drtio_cri = [] for i in range(len(self.drtio_transceiver.channels)): coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtioaux_csr_group.append(coreaux_name) drtioaux_memory_group.append(memory_name) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) # Satellite if i == 0: self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr( DRTIOSatellite(self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") # Repeaters else: corerep_name = "drtiorep" + str(i - 1) drtiorep_csr_group.append(corerep_name) core = cdr( DRTIORepeater(self.rtio_tsc, self.drtio_transceiver.channels[i])) setattr(self.submodules, corerep_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800 * i self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) self.config["RTIO_FREQUENCY"] = str( self.drtio_transceiver.rtio_clk_freq / 1e6) # Si5324 Phaser self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin_33"), rx_synchronizer=self.rx_synchronizer, ultrascale=False, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324_33").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")), platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) ] rtio_clk_period = 1e9 / self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) gtx0 = self.drtio_transceiver.gtxs[0] platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gtx0.txoutclk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel # (Each channel performs single-lane phase alignment for RX) for gtx in self.drtio_transceiver.gtxs[1:]: platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gtx.rxoutclk) self.submodules.rtio_crg = RTIOClockMultiplier( self.drtio_transceiver.rtio_clk_freq) self.csr_devices.append("rtio_crg") fix_serdes_timing_path(platform)