def __init__(self, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ethmac_nrxslots=4, ethmac_ntxslots=4, **kwargs) AMPSoC.__init__(self) add_identifier(self) platform = self.platform rtio_clk_freq = 150e6 # forward RTM UART to second FTDI UART channel serial_1 = platform.request("serial", 1) serial_rtm = platform.request("serial_rtm") self.comb += [ serial_1.tx.eq(serial_rtm.rx), serial_rtm.tx.eq(serial_1.rx) ] self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.comb += platform.request("sfp_tx_disable", 1).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("cdr_clk_clean", 0), data_pads=[platform.request("sfp", 1)] + # 6 and not 8 to work around Vivado bug (Xilinx CR 1020646) [platform.request("rtm_gth", i) for i in range(6)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) drtio_csr_group = [] drtioaux_csr_group = [] drtioaux_memory_group = [] drtio_cri = [] for i in range(len(self.drtio_transceiver.channels)): core_name = "drtio" + str(i) coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtio_csr_group.append(core_name) drtioaux_csr_group.append(coreaux_name) drtioaux_memory_group.append(memory_name) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) core = cdr( DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i])) setattr(self.submodules, core_name, core) drtio_cri.append(core.cri) self.csr_devices.append(core_name) coreaux = cdr(DRTIOAuxController(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800 * i self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) rtio_clk_period = 1e9 / rtio_clk_freq gth0 = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth0.txoutclk, rtio_clk_period / 2) platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth0.txoutclk, gth0.rxoutclk) for gth in self.drtio_transceiver.gths[1:]: platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth0.txoutclk, gth.rxoutclk) self.rtio_channels = rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_serdes_ultrascale.Output(4, sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_serdes_ultrascale.InOut(4, sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) platform.add_extension(fmcdio_vhdci_eem.io) platform.add_connectors(fmcdio_vhdci_eem.connectors) fmcdio_dirctl = platform.request("fmcdio_dirctl") for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch: phy = ttl_simple.Output(s) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output, iostandard="LVDS") eem.Urukul.add_std(self, 0, 1, ttl_simple.Output, iostandard="LVDS") eem.Zotino.add_std(self, 3, ttl_simple.Output, iostandard="LVDS") workaround_us_lvds_tristate(platform) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA( self.get_native_sdram_if())) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri] + drtio_cri, enable_routing=True) self.register_kernel_cpu_csrdevice("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table")
def __init__(self, with_sawg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, **kwargs) RTMCommon.__init__(self) add_identifier(self, suffix=".without-sawg" if not with_sawg else "") self.config["HMC830_REF"] = "150" platform = self.platform rtio_clk_freq = 150e6 rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_serdes_ultrascale.Output(4, sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_serdes_ultrascale.InOut(4, sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG( platform, use_rtio_clock=True) if with_sawg: cls = AD9154 else: cls = AD9154NoSAWG self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0) self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1) self.csr_devices.append("ad9154_crg") self.csr_devices.append("ad9154_0") self.csr_devices.append("ad9154_1") self.config["HAS_AD9154"] = None self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"]) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend( rtio.Channel.from_phy(phy) for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs for phy in sawg.phys) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") drtio_data_pads = [platform.request("sfp", 0)] if self.hw_rev == "v2.0": drtio_data_pads.append(platform.request("rtm_amc_link")) self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("cdr_clk_clean"), data_pads=drtio_data_pads, sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtiosat = rx0( DRTIOSatellite(self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) self.csr_devices.append("drtiosat") self.submodules.drtioaux0 = rx0( DRTIOAuxController(self.drtiosat.link_layer)) self.csr_devices.append("drtioaux0") self.add_wb_slave(self.mem_map["drtioaux"], 0x800, self.drtioaux0.bus) self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtioaux", ["drtioaux0"]) self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"]) self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) self.comb += [ self.drtiosat.cri.connect(self.local_io.cri), self.drtiosat.async_errors.eq(self.local_io.async_errors), ] self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, ultrascale=True, rtio_clk_freq=rtio_clk_freq) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( platform.request("dac_sysref"), self.rtio_tsc.coarse_ts) self.csr_devices.append("sysref_sampler") self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref) self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref) rtio_clk_period = 1e9 / rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period / 2) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk) # placeholder code to test I/O routing and standards if self.hw_rev == "v2.0": self.clock_domains.cd_ddmtd_helper = ClockDomain(reset_less=True) helper_clk = platform.request("ddmtd_helper_clk") self.specials += Instance("IBUFGDS", i_I=helper_clk.p, i_IB=helper_clk.n, o_O=self.cd_ddmtd_helper.clk) ddmtd = platform.request("ddmtd_results") self.sync.ddmtd_helper += platform.request("tp16").eq( ddmtd.rec_clk ^ ddmtd.main_xo)
def __init__(self, with_sawg, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ethmac_nrxslots=4, ethmac_ntxslots=4, **kwargs) AMPSoC.__init__(self) RTMCommon.__init__(self) add_identifier(self, suffix=".without-sawg" if not with_sawg else "") self.config["HMC830_REF"] = "100" platform = self.platform rtio_clk_freq = 150e6 self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_SAYMA_REF"] = None self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) # ensure pins are properly biased and terminated si5324_clkout = platform.request("cdr_clk_clean", 0) self.specials += Instance("IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n, attr={("DONT_TOUCH", "true")}) self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform) self.csr_devices.append("ad9154_crg") self.comb += [ platform.request("sfp_tx_disable", i).eq(0) for i in range(2) ] self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=self.ad9154_crg.refclk, data_pads=[platform.request("sata")] + [platform.request("sfp", i) for i in range(2)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) drtio_csr_group = [] drtioaux_csr_group = [] drtioaux_memory_group = [] drtio_cri = [] for i in range(3): core_name = "drtio" + str(i) coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtio_csr_group.append(core_name) drtioaux_csr_group.append(coreaux_name) drtioaux_memory_group.append(memory_name) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) core = cdr( DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i])) setattr(self.submodules, core_name, core) drtio_cri.append(core.cri) self.csr_devices.append(core_name) coreaux = cdr(DRTIOAuxController(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) memory_address = self.mem_map["drtioaux"] + 0x800 * i self.add_wb_slave(memory_address, 0x800, coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) rtio_clk_period = 1e9 / rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period / 2) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) self.drtio_transceiver.cd_rtio.clk.attr.add("keep") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk) for gth in self.drtio_transceiver.gths[1:]: platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.rxoutclk) platform.add_false_path_constraints( self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk) platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk, self.drtio_transceiver.cd_rtio.clk) rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_serdes_ultrascale.Output(4, sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_serdes_ultrascale.InOut(4, sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) if with_sawg: cls = AD9154 else: cls = AD9154NoSAWG self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0) self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1) self.csr_devices.append("ad9154_0") self.csr_devices.append("ad9154_1") self.config["HAS_AD9154"] = None self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"]) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend( rtio.Channel.from_phy(phy) for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs for phy in sawg.phys) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA( self.get_native_sdram_if())) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri] + drtio_cri, enable_routing=True) self.register_kernel_cpu_csrdevice("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( platform.request("dac_sysref"), self.rtio_tsc.coarse_ts) self.csr_devices.append("sysref_sampler") self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref) self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)