def send_mail_to_user(reciever_email, confirmation_url):
cons = Constant()
sendgrid_object = sendgrid.SendGridAPIClient(apikey=cons.sendgrid_API_key)
data = {
"personalizations": [
{
"to": [
{
"email": reciever_email
}
],
"subject": "Confirm account"
}
],
"from": {
"email": "*****@*****.**",
"name": "Svoop"
},
"content": [
{
"type": "text/html",
"value": cons.email_template(confirmation_url)
}
]
}
response = sendgrid_object.client.mail.send.post(request_body=data)
def udp_server_concurrency(self):
while True:
recv_msg, recv_addr = self.udp_socket.recvfrom(1024)
msg = recv_msg.decode('utf-8')
self.msg = '来自IP:{}端口:{}:\n{}\n'.format(recv_addr[0], recv_addr[1],
msg)
self.signal_write_msg.emit("写入")
Constant.parse_receive(self.msg)
def __init__(self):
""" Inicializa los scopes de las variables : Temporales, Globales,
Locales y Constantes.
"""
self.tmp = Temporal()
self.glob = Globs()
self.loc = Local()
self.const = Constant()
self.max_memory = 20000
self.current_used_memory = 0
def load_exec(path):
with open(path, 'rb') as f:
# TODO implement an actual binary format
for key, value in pickle.load(f):
key = (Constant(key[0]), key[1])
if key[0] == Constant.SYMBOL:
value = (Constant(value[0]), value[1])
elif key[0] == Constant.CODE and len(value) == 2:
value = tuple(value) + (dict(), ) # Auto-upgrade
elif key[0] == Constant.CODE:
value = (value[0], value[1], dict(value[2]))
yield (key, value)
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
# Fetch
self.PCMux = Mux()
self.ProgramC = PC(long(0xbfc00200))
self.InstMem = InstructionMemory(memoryFile)
self.IFadder = Add()
self.JMux = Mux()
self.IFaddconst = Constant(4)
self.IF_ID_Wall = Wall()
self.fetchgroup = {}
# Decode
self.register = RegisterFile()
self.signext = SignExtender()
self.control = ControlElement()
self.jmpCalc = JumpCalc()
self.ID_EX_Wall = Wall()
# Execute
self.EXadder = Add()
self.shiftL = LeftShifter()
self.ALogicUnit = ALU()
self.ALUSrcMux = Mux()
self.RegDstMux = Mux()
self.ALUctrl = AluControl()
self.EX_MEM_Wall= Wall()
# Memory
self.storage = DataMemory(memoryFile)
self.brnch = Branch()
self.MEM_WB_Wall= Wall()
# Write Back
self.WBmux = Mux()
self.ProgramC
self.elements1 = [self.InstMem, self.IFaddconst, self.IFadder, self.PCMux, self.JMux]
self.elements2 = [self.control, self.register, self.signext, self.jmpCalc]
self.elements3 = [self.shiftL, self.ALUSrcMux, self.RegDstMux, self.ALUctrl, self.ALogicUnit, self.EXadder]
self.elements4 = [self.brnch, self.storage]
self.elementsboot = [self.IFaddconst, self.IFadder, self.InstMem,
self.IF_ID_Wall, self.register, self.signext, self.control, self.jmpCalc,
self.ID_EX_Wall, self.RegDstMux, self.shiftL, self.EXadder, self.ALUSrcMux, self.ALUctrl, self.ALogicUnit,
self.EX_MEM_Wall, self.brnch, self.storage,
self.MEM_WB_Wall, self.WBmux, self.PCMux, self.JMux]
self.walls = [self.MEM_WB_Wall, self.EX_MEM_Wall, self.ID_EX_Wall, self.IF_ID_Wall]
self._connectCPUElements()
def check_term_valid(self, term):
""" Check if term is syntax and semantic valid
Term include 'const', '*', '/'
return :
True, value of term if 'term' is valid
False, None if 'term' is not valid
"""
term_stars = term.split("*")
# IF term is const
if (len(term_stars) == 1): # term == const
term_value = term_stars[0]
is_constant = Constant().check_constant_valid(term_value)
if is_constant == False:
return False, None
else:
return True, term_value
# IF term is not const
for term_star_idx in range(len(term_stars)):
term_star = term_stars[term_star_idx]
term_splashes = term_star.split("/")
for term_splash_idx in range(len(term_splashes)):
# Check syntax
term_splash = term_splashes[term_splash_idx]
if (Constant().check_constant_valid(term_splash) == False):
return False, None
else:
# Check if term_splash must be a number
try:
term_splash = float(term_splash)
except:
return False, None
# Check semantic
if (term_splash_idx == 0):
term_star_value = term_splash
else:
term_star_value = term_star_value / term_splash
# Check semantic
if (term_star_idx == 0):
term_value = term_star_value
else:
term_value = term_value * term_star_value
return True, term_value
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
self.adder = Add()
self.branchAdder = Add()
self.alu = Alu()
self.aluControl = AluControl()
self.branchNE = BranchNotEqual()
self.branch = Branch()
self.constant = Constant(4)
self.control = Control()
self.dataMemory = DataMemory(memoryFile)
self.instructionMemory = InstructionMemory(memoryFile)
self.regMux = Mux()
self.aluMux = Mux()
self.dmMux = Mux()
self.branchMux = Mux()
self.jmpMux = Mux()
self.registerFile = RegisterFile()
self.shiftLeft2 = ShiftLeft2()
self.signExtend = SignExtend()
self.jump = Jump()
self.leftShift2 = ShiftLeft2()
self.leftShift2Jump = ShiftLeft2Jump()
self.IFID = IFID()
self.IDEX = IDEX()
self.EXMEM = EXMEM()
self.MEMWB = MEMWB()
self.pc = PC(0xbfc00200) # hard coded "boot" address
self.IFIDelements = [ self.constant, self.branchMux, self.jmpMux, self.instructionMemory, self.adder ]
self.IDEXelements = [ self.control, self.registerFile, self.signExtend, self.leftShift2Jump, self.jump ]
self.EXMEMelements = [ self.regMux, self.aluControl, self.aluMux, self.alu, self.shiftLeft2, self.branchAdder, self.branchNE, self.branch ]
self.MEMWBelements = [ self.dataMemory ]
self.WBelements = [ self.dmMux ]
self.elements = [ self.IFIDelements, self.IDEXelements, self.EXMEMelements, self.WBelements]
self.pipes = [ self.IFID, self.IDEX, self.EXMEM, self.MEMWB]
self._connectCPUElements()
def tcp_client_concurrency(self):
"""
功能函数，用于TCP客户端创建子线程的方法，阻塞式接收
:return:
"""
while True:
recv_msg = self.tcp_socket.recv(1024)
if recv_msg:
msg = recv_msg.decode('utf-8')
self.msg = '来自IP:{}端口:{}:\n{}\n'.format(
self.address[0], self.address[1], msg)
self.signal_write_msg.emit("写入")
Constant.parse_receive(self.msg)
else:
self.tcp_socket.close()
self.reset()
self.msg = '从服务器断开连接\n'
self.signal_write_msg.emit("写入")
break
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
self.dataMemory = DataMemory(memoryFile)
self.instructionMemory = InstructionMemory(memoryFile)
self.registerFile = RegisterFile()
self.constant3 = Constant(3)
self.constant4 = Constant(4)
self.randomControl = RandomControl()
self.mux = Mux()
self.adder = Add()
self.pc = PC(0xbfc00000) # hard coded "boot" address
self.elements = [
self.constant3, self.constant4, self.randomControl, self.adder,
self.mux
]
self._connectCPUElements()
def web_server_concurrency(self):
"""
功能函数，供创建线程的方法；
使用子线程用于监听并创建连接，使主线程可以继续运行，以免无响应
使用非阻塞式并发用于接收客户端消息，减少系统资源浪费，使软件轻量化
:return:None
"""
while True:
try:
self.client_socket, self.client_address = self.tcp_socket.accept(
)
except Exception as ret:
pass
else:
self.client_socket.setblocking(False)
# 将创建的客户端套接字存入列表
self.client_socket_list.append(
(self.client_socket, self.client_address))
self.msg = 'WEB服务端已连接浏览器，IP:%s端口:%s\n' % self.client_address
self.signal_write_msg.emit("写入")
# 轮询客户端套接字列表，接收数据
for client, address in self.client_socket_list:
try:
recv_msg = client.recv(1024)
except Exception as ret:
pass
else:
if recv_msg:
msg = recv_msg.decode('utf-8')
msg_lines = msg.splitlines()
msg_dir = re.match(r"[^/]+(/[^ ]*)", msg_lines[0])
self.msg_dir = msg_dir.group(1)
self.msg = '来自IP:{}端口:{}:\n请求路径:{}\n'.format(
address[0], address[1], self.msg_dir)
self.signal_write_msg.emit("写入")
Constant.parse_receive(self.msg)
self.web_client_socket = client
self.all_send()
else:
client.close()
self.client_socket_list.remove((client, address))
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
self.datamemory = DataMemory(memoryFile)
self.instructionmemory = InstructionMemory(memoryFile)
self.registerfile = RegisterFile()
self.constant4 = Constant(4)
self.alu = Alu()
self.controlunit = ControlUnit()
self.shift2 = Shift2()
self.shift16 = Shift16()
self.signextend = SignExtend()
self.alterand = Alterand()
self.altershift = Altershift()
self.mux_writereg = Mux() # 6 multiplexors
self.mux_regoutput = Mux()
self.mux_jump = Mux()
self.mux_branch = Mux()
self.mux_datamem = Mux()
self.mux_shift16 = Mux()
self.adderpc = Add() # 2 adders
self.addershift = Add()
self.pc = PC(0xbfc00000) # hard coded "boot" address
self.elements = [
self.constant4, self.adderpc, self.instructionmemory,
self.controlunit, self.altershift, self.mux_writereg,
self.registerfile, self.shift16, self.signextend, self.shift2,
self.addershift, self.mux_regoutput, self.alu, self.alterand,
self.mux_branch, self.mux_jump, self.datamemory, self.mux_datamem,
self.mux_shift16, self.registerfile
]
self._connectCPUElements()
def main():
symbol_table = SymbolTable()
v1 = Identifier('a', 5)
v2 = Identifier('b', 7)
v3 = Identifier('c', 12)
v4 = Identifier('a', 14)
c1 = Constant('d', 7)
symbol_table.add(v1)
symbol_table.add(v2)
symbol_table.add(v3)
symbol_table.add(c1)
symbol_table.add(v4)
v2.set_value(42)
symbol_table.add(v2)
c2 = Constant('c', 17)
symbol_table.add(c2)
symbol_table.print_symbol_table()
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
self.dataMemory = DataMemory(memoryFile)
self.instructionMemory = InstructionMemory(memoryFile)
self.registerFile = RegisterFile()
self.alu = ALU()
self.mainControl = MainControl()
self.splitter = Splitter()
self.signExtender = SignExtender()
self.andGate = AndGate()
self.breaker = Breaker()
self.constant4 = Constant(4)
# self.randomControl = RandomControl()
self.pcMux1 = Mux()
self.pcMux2 = Mux()
self.regMux = Mux()
self.aluMux = Mux()
self.resultMux = Mux()
self.luiMux = Mux()
self.adder = Add()
self.branchAdder = Add()
self.jumpAddress = JMPAddress()
self.shiftBranch = LeftShiftTwo()
self.shiftJump = LeftShiftTwo()
self.pc = PC(hex(0xbfc00000)) # hard coded "boot" address
self.elements = [self.constant4, self.adder, self.instructionMemory, self.breaker, self.splitter,
self.shiftJump, self.mainControl, self.regMux, self.signExtender, self.luiMux, self.registerFile,
self.jumpAddress, self.shiftBranch, self.branchAdder, self.aluMux, self.alu, self.dataMemory,
self.andGate, self.pcMux1, self.pcMux2, self.resultMux, self.registerFile, self.pc]
self._connectCPUElements()
def tcp_server_concurrency(self):
"""
功能函数，供创建线程的方法；
使用子线程用于监听并创建连接，使主线程可以继续运行，以免无响应
使用非阻塞式并发用于接收客户端消息，减少系统资源浪费，使软件轻量化
:return:None
"""
while True:
try:
self.client_socket, self.client_address = self.tcp_socket.accept(
)
except Exception as ret:
pass
else:
self.client_socket.setblocking(False)
# 将创建的客户端套接字存入列表
self.client_socket_list.append(
(self.client_socket, self.client_address))
self.msg = 'TCP服务端已连接IP:%s端口:%s\n' % self.client_address
self.signal_write_msg.emit("写入")
# 轮询客户端套接字列表，接收数据
for client, address in self.client_socket_list:
try:
recv_msg = client.recv(1024)
except Exception as ret:
pass
else:
if recv_msg:
msg = recv_msg.decode('utf-8')
self.msg = '来自IP:{}端口:{}:\n{}\n'.format(
address[0], address[1], msg)
self.signal_write_msg.emit("写入")
Constant.parse_receive(self.msg)
else:
client.close()
self.client_socket_list.remove((client, address))
def main_menu():
global screen
cons = Constant()
menu_song = pygame.mixer.music.load(path.join(sound_folder, "menu.mp3"))
pygame.mixer.music.set_volume(5)
pygame.mixer.music.play(-1)
title = pygame.image.load(path.join(img_dir, "main.jpg")).convert()
title = pygame.transform.scale(title, (cons.WIDTH, cons.HEIGHT), screen)
screen.blit(title, (0,0))
draw_text(screen, "School Battle", 72, cons.WIDTH/2, cons.HEIGHT/2 - 80, cons.BLACK)
pygame.display.update()
while True:
ev = pygame.event.poll()
if ev.type == pygame.KEYDOWN:
if ev.key == pygame.K_RETURN:
break
elif ev.key == pygame.K_q:
pygame.quit()
quit()
elif ev.type == pygame.QUIT:
pygame.quit()
quit()
else:
draw_text(screen, "Press [ENTER] To Begin", 30, cons.WIDTH/2, cons.HEIGHT/2, cons.BLACK)
draw_text(screen, "or [Q] To Quit", 30, cons.WIDTH/2, (cons.HEIGHT/2)+40, cons.BLACK)
draw_text(screen, "Press [SPACE] To Shoot", 30, cons.WIDTH/2, cons.HEIGHT/2 + 80, cons.BLACK)
pygame.display.update()
# Hide the mouse cursor.
pygame.mouse.set_visible(False)
screen.fill(cons.BLACK)
screen.blit(background, background_rect)
draw_text(screen, "GET READY!", 40, cons.WIDTH/2, cons.HEIGHT/2, cons.BLACK)
pygame.display.update()
pygame.event.pump()
pygame.time.wait(1000)
for i in range(3):
screen.fill(cons.BLACK)
screen.blit(background, background_rect)
draw_text(screen, str(3 - i), 40, cons.WIDTH/2, cons.HEIGHT/2, cons.BLACK)
pygame.display.update()
pygame.event.pump()
pygame.time.wait(1000)
def decode_constant_pool(data, count):
# 0th entry is a sentinel, since constants are indexed 1..constant_pool_size
constants = [None]
offset = 0
skip = False
for k in range(1, count):
if skip:
skip = False
continue
constant = Constant.parse(data[offset:])
constants.append(constant)
offset += constant.size()
# special cases for Long/Double constants!
# http://java.sun.com/docs/books/jvms/second_edition/html/ClassFile.doc.html#1348
if isinstance(constant, (LongConstant, DoubleConstant)):
constants.append(None) # append a sentinel
skip = True
return constants, data[offset:]
def decode_constant_pool(data, count):
# 0th entry is a sentinel, since constants are indexed 1..constant_pool_size
constants = [None]
offset = 0
skip = False
for k in range(1, count):
if skip:
skip = False
continue
constant = Constant.parse(data[offset:])
constants.append(constant)
offset += constant.size()
# special cases for Long/Double constants!
# http://java.sun.com/docs/books/jvms/second_edition/html/ClassFile.doc.html#1348
if isinstance(constant, (LongConstant, DoubleConstant)):
constants.append(None) # append a sentinel
skip = True
return constants, data[offset:]
def static_dielectric_constant(self):
"""Calculate relative static dielectric constant (w=0)
Ref: Mol. Phys. 50, 841-858 (1983)
Returns
-------
dielec_const_vec : float[:], shape = (num_frame)
relative dielectric constant.
"""
const = Constant()
tot_dip_mat = self.total_dipole()
run_avg_dip_vec = self._running_mean(np.sum(tot_dip_mat[:,:3], axis=1))
run_avg_sqr_dip_vec = self._running_mean(np.sum(tot_dip_mat[:,:3]**2, axis=1))
vol_vec = self._box_mat[:,0]*self._box_mat[:,1]*self._box_mat[:,2]
dielec_const_vec = np.zeros(self._num_frame)
dielec_const_vec.fill(4*np.pi/3)
dielec_const_vec *= run_avg_sqr_dip_vec - run_avg_dip_vec**2
dielec_const_vec /= vol_vec*const.kB*300
dielec_const_vec /= const.eps0*1e-10/(1.602*1.602*1e-38)
dielec_const_vec += 1
return(dielec_const_vec)
class World:
def __init__(self):
self.log = Logging()
self.constant = Constant()
self.maps = {} # ID(int), MAP(object)
def createWorld(self):
self.log.info(35 * '-')
self.log.info('Creation of the world begins:')
# --------------------------------------------------------------------
# Players data are loading here
self.playersData = dataSource.PlayersData()
self.playersData.load_in_to_class()
self.playersData = self.playersData.get_player_data()
self.log.info('Player were loaded')
# --------------------------------------------------------------------
# Maps data are loaded here
__mapData = dataSource.MapData()
__mapData.load_in_to_class()
__mapData = __mapData.get_map_data()
for __mapId, __mapObject in __mapData.items():
self.add_map(__mapId, __mapObject)
del __mapData, __mapId, __mapObject
self.log.info('Maps were loaded')
self.log.info('The world-server has finished loading')
self.log.info(35 * '-')
def add_map(self, id, mapObject):
self.maps[id] = mapObject
def get_map(self, id):
return self.maps.get(id)
def get_players(self):
return self.playersData
def get_players_by_accid(self, accId):
__playerList = {}
__position = 1
for player in self.playersData:
if player.get_account_id() == accId:
__playerList[__position] = player
__position += 1
return __playerList
def create_player(self, accId, name, pClass, sex, color1, color2, color3):
__playerID = 0
for player in self.playersData:
if player.get_id() > __playerID:
__playerID = player.get_id()
__playerID = __playerID + 1
__startMapCellList = self.constant.get_start_map_incarnam(pClass)
player = Player(
__playerID,
name,
accId,
-1, # id, name, account, group,
sex,
pClass,
color1,
color2,
color3, # sexe, pClass, color1-3,
0,
1,
'',
10000,
1, # kamas, spellboost, capital, energy, level,
#0, 100, pClass * 10 + sex, # xp, size, gfx,
0,
100,
(pClass * 10 + sex), # xp, size, gfx,
0,
0,
0,
0, # alignement, honor, deshonor, alvl,
[0, 0, 0, 0, 0, 0],
1,
0, # stats(list), seeFriend, seeAlign,
0,
'*#$p^',
__startMapCellList[0], # seeSeller, channel, map,
__startMapCellList[1],
100, # cell, pdvper,
'141;', # spells <-- TODO placeholder
'',
'', # objets, storeObjets,
str(__startMapCellList[0]) + ':' +
str(__startMapCellList[1]), # savepos
'',
'',
0, # zaaps, jobs, mountxpgive,
0,
0,
'0;0', # title, wife, morphMode,
'',
0,
1, # emotes, prison, server, <-- TODO placeholder
True,
'', # logged allTitle
'118,0;119,0;123,0;124,0;125,0;126,0',
0,
0,
) # parcho, timeDeblo, noall
del __startMapCellList
self.playersData.append(player)
def delete_player(self, __playerID):
# TODO remove player from his guild
# TODO remove all his objets
# determination of the list position
__listPosition = 0
for player in self.playersData:
if player.get_id() == __playerID:
break
else:
__listPosition += 1
# delete list entry (in self.playersData)
del self.playersData[__listPosition]
from averager import Averager
from constant import Constant
from julia import Competative
from zeke import Zeke
from regression import Regression
from alice import Alice
from julia import Julia
from marginal import Marginal
from julia import Julinear
players = [
Laster(),
Zeke(),
Julia(),
Julinear(),
Constant(),
Competative(),
Marginal()
]
TheGov = Gov(players, plant_groups)
Plotter = MultiGraphPlotter(window=100)
MoneyPlotter = PlayerStatePlotter(window=100)
# The number of times to repeat the simulation.
repeats = 50
# The number of rounds per simulation.
rounds = 24 * 365
# Rather or not we should plot.
plot = False
class MySimulator():
'''Main class for MIPS pipeline simulator.
Provides the main method tick(), which runs pipeline
for one clock cycle.
'''
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
self.datamemory = DataMemory(memoryFile)
self.instructionmemory = InstructionMemory(memoryFile)
self.registerfile = RegisterFile()
self.constant4 = Constant(4)
self.alu = Alu()
self.controlunit = ControlUnit()
self.shift2 = Shift2()
self.shift16 = Shift16()
self.signextend = SignExtend()
self.alterand = Alterand()
self.altershift = Altershift()
self.mux_writereg = Mux() # 6 multiplexors
self.mux_regoutput = Mux()
self.mux_jump = Mux()
self.mux_branch = Mux()
self.mux_datamem = Mux()
self.mux_shift16 = Mux()
self.adderpc = Add() # 2 adders
self.addershift = Add()
self.pc = PC(0xbfc00000) # hard coded "boot" address
self.elements = [
self.constant4, self.adderpc, self.instructionmemory,
self.controlunit, self.altershift, self.mux_writereg,
self.registerfile, self.shift16, self.signextend, self.shift2,
self.addershift, self.mux_regoutput, self.alu, self.alterand,
self.mux_branch, self.mux_jump, self.datamemory, self.mux_datamem,
self.mux_shift16, self.registerfile
]
self._connectCPUElements()
def _connectCPUElements(self):
self.constant4.connect([], ['constant'], [], [])
self.controlunit.connect(
[(self.instructionmemory, 'ins_31-26'),
(self.instructionmemory, 'ins_5-0')], [], [], [
'regdst', 'jump', 'branch', 'memread', 'memtoreg', 'aluop',
'memwrite', 'alusrc', 'regwrite', 'branchnotequal', 'loadui'
])
self.adderpc.connect([(self.pc, 'pcaddress'),
(self.constant4, 'constant')], ['sum_pc'], [],
[])
self.instructionmemory.connect([(self.pc, 'pcaddress')], [
'ins_31-26', 'ins_25-21', 'ins_20-16', 'ins_15-11', 'ins_15-0',
'ins_5-0', 'ins_25-0'
], [], [])
self.altershift.connect([(self.instructionmemory, 'ins_25-0'),
(self.adderpc, 'sum_pc')], ['jump_address'],
[], [])
self.signextend.connect([(self.instructionmemory, 'ins_15-0')],
['signextend_result'], [], [])
self.shift2.connect([(self.signextend, 'signextend_result')],
['shift2_result'], [], [])
self.addershift.connect([(self.adderpc, 'sum_pc'),
(self.shift2, 'shift2_result')],
['sum_addershift'], [], [])
self.mux_branch.connect([(self.adderpc, 'sum_pc'),
(self.addershift, 'sum_addershift')],
['mux_branch_result'],
[(self.alterand, 'alterand_result')], [])
self.mux_jump.connect([(self.mux_branch, 'mux_branch_result'),
(self.altershift, 'jump_address')],
['mux_jump_result'],
[(self.controlunit, 'jump')], [])
self.alterand.connect([], [], [(self.controlunit, 'branch'),
(self.controlunit, 'branchnotequal'),
(self.alu, 'alu_zero_result')],
['alterand_result'])
self.mux_writereg.connect([(self.instructionmemory, 'ins_20-16'),
(self.instructionmemory, 'ins_15-11')],
['mux_writereg_result'],
[(self.controlunit, 'regdst')], [])
self.registerfile.connect([(self.instructionmemory, 'ins_25-21'),
(self.instructionmemory, 'ins_20-16'),
(self.mux_writereg, 'mux_writereg_result'),
(self.mux_shift16, 'mux_shift16_result')],
['reg_data1', 'reg_data2'],
[(self.controlunit, 'regwrite')], [])
self.mux_regoutput.connect([(self.registerfile, 'reg_data2'),
(self.signextend, 'signextend_result')],
['mux_regoutput_result'],
[(self.controlunit, 'alusrc')], [])
self.alu.connect([(self.registerfile, 'reg_data1'),
(self.mux_regoutput, 'mux_regoutput_result')],
['alu_result'], [(self.controlunit, 'aluop')],
['alu_zero_result'])
self.datamemory.connect([(self.alu, 'alu_result'),
(self.registerfile, 'reg_data2')],
['datamemory_result'],
[(self.controlunit, 'memwrite'),
(self.controlunit, 'memread')], [])
self.mux_datamem.connect([(self.alu, 'alu_result'),
(self.datamemory, 'datamemory_result')],
['mux_datamemory_result'],
[(self.controlunit, 'memtoreg')], [])
self.mux_shift16.connect([(self.mux_datamem, 'mux_datamemory_result'),
(self.shift16, 'shift16_result')],
['mux_shift16_result'],
[(self.controlunit, 'loadui')], [])
self.shift16.connect([(self.instructionmemory, 'ins_15-0')],
['shift16_result'], [], [])
self.pc.connect([(self.mux_jump, 'mux_jump_result')], ['pcaddress'],
[], [])
def clockCycles(self):
'''Returns the number of clock cycles spent executing instructions.'''
return self.nCycles
def dataMemory(self):
'''Returns dictionary, mapping memory addresses to data, holding
data memory after instructions have finished executing.'''
return self.dataMemory.memory
def registerFile(self):
'''Returns dictionary, mapping register numbers to data, holding
register file after instructions have finished executing.'''
return self.registerfile.register
def printDataMemory(self):
self.dataMemory.printAll()
def printRegisterFile(self):
self.registerfile.printAll()
def tick(self):
'''Execute one clock cycle of pipeline.'''
self.nCycles += 1
# The following is just a small sample implementation
self.pc.writeOutput()
for elem in self.elements:
elem.readControlSignals()
elem.readInput()
elem.writeOutput()
elem.setControlSignals()
self.pc.readInput()
import math, argparse
import numpy as np
import tensorflow as tf
import tensorflow_hub as hub
import os
import nltk
nltk.download('punkt')
nltk.download('averaged_perceptron_tagger')
nltk.download('universal_tagset')
from nltk import pos_tag, word_tokenize, RegexpParser
from constant import Constant
const = Constant()
const.MODULE_URL = "https://tfhub.dev/google/universal-sentence-encoder-large/5" #@param ["https://tfhub.dev/google/universal-sentence-encoder/2", "https://tfhub.dev/google/universal-sentence-encoder-large/3"]
# os.environ['TFHUB_CACHE_DIR'] = '/tmp/tfhub_modules'
print('start')
embed = hub.load(const.MODULE_URL)
def similarities(sentence, paraphrases):
vectors = embed([sentence] + paraphrases)
cosine_similarities = []
for v2 in vectors[1:]:
cosine_similarities.append(
cosine_similarity(np.array(vectors[0]), np.array(v2)))
return cosine_similarities
def similarity(sentence, paraphrase):
vectors = embed([sentence, paraphrase])
class MIPSSimulator():
'''Main class for MIPS pipeline simulator.
Provides the main method tick(), which runs pipeline
for one clock cycle.
'''
def __init__(self, memoryFile):
self.nCycles = 1 # Used to hold number of clock cycles spent executing instructions
self.adder = Add()
self.branchAdder = Add()
self.alu = Alu()
self.aluControl = AluControl()
self.branchNE = BranchNotEqual()
self.branch = Branch()
self.constant = Constant(4)
self.control = Control()
self.dataMemory = DataMemory(memoryFile)
self.instructionMemory = InstructionMemory(memoryFile)
self.regMux = Mux()
self.aluMux = Mux()
self.dmMux = Mux()
self.branchMux = Mux()
self.jmpMux = Mux()
self.registerFile = RegisterFile()
self.shiftLeft2 = ShiftLeft2()
self.signExtend = SignExtend()
self.jump = Jump()
self.leftShift2 = ShiftLeft2()
self.leftShift2Jump = ShiftLeft2Jump()
self.pc = PC(0xbfc00000) # hard coded "boot" address
self.elements = [
self.constant, self.adder, self.instructionMemory, self.control,
self.regMux, self.leftShift2Jump, self.jump, self.registerFile,
self.signExtend, self.shiftLeft2, self.branchAdder, self.aluMux,
self.aluControl, self.alu, self.branchNE, self.branch,
self.branchMux, self.jmpMux, self.dataMemory, self.dmMux
]
self._connectCPUElements()
def _connectCPUElements(self):
self.pc.connect([(self.jmpMux, 'newAddress')], ['address'], [], [])
self.constant.connect([], ['constant'], [], [])
self.adder.connect([(self.constant, 'constant'), (self.pc, 'address')],
['sum'], [], [])
self.instructionMemory.connect(
[(self.pc, 'address')], ['op', 'rs', 'rt', 'rd', 'shamt', 'funct'],
[], [])
self.control.connect([(self.instructionMemory, 'op')], [], [], [
'regDst', 'aluSrc', 'memtoReg', 'regWrite', 'memRead', 'memWrite',
'branch', 'aluOp1', 'aluOp0', 'bne', 'jump'
])
self.regMux.connect([(self.instructionMemory, 'rt'),
(self.instructionMemory, 'rd')], ['wrSignal'],
[(self.control, 'regDst')], [])
self.leftShift2Jump.connect([(self.instructionMemory, 'rs'),
(self.instructionMemory, 'rt'),
(self.instructionMemory, 'rd'),
(self.instructionMemory, 'shamt'),
(self.instructionMemory, 'funct')],
['jmpAddress'], [], [])
self.jump.connect([(self.leftShift2Jump, 'jmpAddress'),
(self.adder, 'sum')], ['newJmp'], [], [])
self.registerFile.connect([(self.instructionMemory, 'rs'),
(self.instructionMemory, 'rt'),
(self.regMux, 'wrSignal'),
(self.dmMux, 'regWrite')], ['rd1', 'rd2'],
[(self.control, 'regWrite')], [])
self.signExtend.connect([(self.instructionMemory, 'rd'),
(self.instructionMemory, 'shamt'),
(self.instructionMemory, 'funct')],
['extendedOutput'], [], [])
self.shiftLeft2.connect([(self.signExtend, 'extendedOutput')],
['toBAdder'], [], [])
self.branchAdder.connect([(self.adder, 'sum'),
(self.shiftLeft2, 'toBAdder')],
['bAdderResult'], [], [])
self.aluMux.connect([(self.registerFile, 'rd1'),
(self.signExtend, 'extendedOutput')], ['toAlu'],
[(self.control, 'aluSrc')], [])
self.aluControl.connect([(self.instructionMemory, 'funct')], [],
[(self.control, 'aluOp0'),
(self.control, 'aluOp1')],
['aluControlSignal'])
self.alu.connect([(self.registerFile, 'rd1'),
(self.aluMux, 'toAlu')], ['aluResult'],
[(self.aluControl, 'aluControlSignal')], ['zero'])
self.branchNE.connect([], [], [(self.control, 'bne'),
(self.alu, 'zero')], ['inverted'])
self.branch.connect([], [], [(self.control, 'branch'),
(self.branchNE, 'inverted')],
['branched'])
self.branchMux.connect([(self.adder, 'sum'),
(self.branchAdder, 'bAdderResult')],
['bMuxOutput'], [(self.branch, 'branched')], [])
self.jmpMux.connect([(self.branchMux, 'bMuxOutput'),
(self.jump, 'newJmp')], ['newAddress'],
[(self.control, 'jump')], [])
self.dataMemory.connect([(self.alu, 'aluResult'),
(self.registerFile, 'rd2')], ['rd'],
[(self.control, 'memWrite'),
(self.control, 'memRead')], [])
self.dmMux.connect([(self.dataMemory, 'rd'), (self.alu, 'aluResult')],
['regWrite'], [(self.control, 'memtoReg')], [])
def clockCycles(self):
'''Returns the number of clock cycles spent executing instructions.'''
return self.nCycles
def dataMemory(self):
'''Returns dictionary, mapping memory addresses to data, holding
data memory after instructions have finished executing.'''
return self.dataMemory.memory
def registerFile(self):
'''Returns dictionary, mapping register numbers to data, holding
register file after instructions have finished executing.'''
return self.registerFile.register
def printDataMemory(self):
self.dataMemory.printAll()
def printRegisterFile(self):
self.registerFile.printAll()
def tick(self):
'''Execute one clock cycle of pipeline.'''
self.nCycles += 1
# The following is just a small sample implementation
self.pc.writeOutput()
for elem in self.elements:
elem.readControlSignals()
elem.readInput()
elem.writeOutput()
elem.setControlSignals()
self.pc.readInput()
class memory_manager():
def __init__(self):
""" Inicializa los scopes de las variables : Temporales, Globales,
Locales y Constantes.
"""
self.tmp = Temporal()
self.glob = Globs()
self.loc = Local()
self.const = Constant()
self.max_memory = 20000
self.current_used_memory = 0
def increment_address_pointer(self, var_type, var_dir, offset):
""" Almacenar y manejar direcciones de arreglos.
Args:
var_dir: Diccionario del tipo de dato.
var_type: Tipo de dato de la variable.
offset: Tamanio del arreglo.
"""
# Checar la direccion y si cabe dentro de los limites de la memoria entonces
# incrementar el contador de ese scope en la cantidad de casillas del arreglo.
if var_dir >= self.tmp.l_limit and var_dir <= self.tmp.u_limit:
self.tmp.increment_address_pointer(var_dir, var_type, offset)
elif var_dir >= self.glob.l_limit and var_dir <= self.glob.u_limit:
self.glob.increment_address_pointer(var_dir, var_type, offset)
elif var_dir >= self.loc.l_limit and var_dir <= self.loc.u_limit:
self.loc.increment_address_pointer(var_dir, var_type, offset)
elif var_dir >= self.const.l_limit and var_dir <= self.const.u_limit:
self.const.increment_address_pointer(var_dir, var_type, offset)
def set_val(self, var_dir, val, var_type):
""" Asignar valor a las direcciones de cada scope.
Args:
var_dir: Direccion de la variable.
val: Valor de la variable.
var_type: Tipo de dato de la variable.
"""
# Checar la direccion y dependiendo del mismo asignarle el valor a la
# direccion de la variable.
if var_dir >= self.tmp.l_limit and var_dir <= self.tmp.u_limit:
self.tmp.set_val(var_dir, val, var_type)
elif var_dir >= self.glob.l_limit and var_dir <= self.glob.u_limit:
self.glob.set_val(var_dir, val, var_type)
elif var_dir >= self.loc.l_limit and var_dir <= self.loc.u_limit:
self.loc.set_val(var_dir, val, var_type)
elif var_dir >= self.const.l_limit and var_dir <= self.const.u_limit:
self.const.set_val(var_dir, val, var_type)
def free_memory(self, no_vars):
""" Libera la memoria que ha sido utilizada por una llamada a funcion.
Args:
no_vars: Cantidad de variables de una funcion. """
self.current_used_memory -= no_vars
def check_available_memory(self, no_vars):
""" Pide la memoria que sera utilizada por una llamada a funcion.
Args:
no_vars: Cantidad de variables de una funcion. """
if self.current_used_memory + no_vars <= self.max_memory:
self.current_used_memory += no_vars
else:
# muestra un error en caso de que ya no haya mas memoria.
raise MemoryError("ERROR: ya no hay espacio en memoria.")
def get_val_from_dir(self, address):
""" Obtener el valor de una direccion.
Args:
address: Direccion de la cual se quiere obtener el valor.
Return:
Valor de la direccion
"""
# Checar si la direccion esta dentro de los limites para ver el scope
# de dato que es para posteriormente obtener la direccion.
# Usar en arreglos (numero)
if str(address)[len(str(address)) - 1] == '_':
return int(address[:len(str(address)) - 1])
# Apuntador a una direccion
if str(address)[0] == '_':
meta_address = self.get_val_from_dir(int(address[1:]))
return self.get_val_from_dir(meta_address)
if address >= self.tmp.l_limit and address <= self.tmp.u_limit:
return self.tmp.get_val_from_dir(address)
elif address >= self.glob.l_limit and address <= self.glob.u_limit:
return self.glob.get_val_from_dir(address)
elif address >= self.loc.l_limit and address <= self.loc.u_limit:
return self.loc.get_val_from_dir(address)
elif address >= self.const.l_limit and address <= self.const.u_limit:
return self.const.get_val_from_dir(address)
def set_val_from_dir(self, address, val):
""" Asignar el valor a una direccion. Si no se encuentra la
direccion entonces mostrar un error.
Args:
address: Direccion de la cual se quiere asignar el valor.
val: Valor a asignar.
"""
# Checar si la direccion esta dentro de los limites para ver el scope
# del dato que es para posteriormente asignarle un valor a la direccion.
# Apuntador a una direccion
if str(address)[0] == '_':
address = self.get_val_from_dir(int(address[1:]))
if address >= self.tmp.l_limit and address <= self.tmp.u_limit:
self.tmp.set_val_from_dir(address, val)
elif address >= self.glob.l_limit and address <= self.glob.u_limit:
self.glob.set_val_from_dir(address, val)
elif address >= self.loc.l_limit and address <= self.loc.u_limit:
self.loc.set_val_from_dir(address, val)
elif address >= self.const.l_limit and address <= self.const.u_limit:
self.const.set_val_from_dir(address, val)
def insert_variable(self, var_type, var_id, var_scope, var_val):
""" Funcion exclusiva para agregar variables locales/globales
Args:
var_type: El tipo de la variable.
var_id: Id de la variable.
var_scope: Scope de la variable.
var_val: Valor de la variable.
"""
global debug
segment = self.check_variable_functionality(var_scope, var_id)
if debug:
print("llego la variable", var_id, "de tipo", var_type,
"para el segmento de", segment)
if var_type == "entero":
return segment.insert_integer(var_val)
elif var_type == "flotante":
return segment.insert_float(var_val, var_id)
elif var_type == "bool":
return segment.insert_boolean(var_val)
elif var_type == "caracter":
return segment.insert_character(var_val)
elif var_type == "cadena":
return segment.insert_string(var_val)
def check_variable_functionality(self, var_scope, var_id):
"""" Revisa si la variable es temporal, global o local
Args:
var_scope: Scope de la variable.
var_id: id de la variable
Regreso:
El objeto correspondiente a la funcionalidad de la variable."""
if var_id == "const":
return self.const
elif var_id[0:2] == "t_":
return self.tmp
elif var_scope == "global":
return self.glob
else:
return self.loc
"""
def addConst(self, val):
if val not in self.consts:
self.consts[val] = Constant(val)
return self.consts[val]
import tensorflow_hub as hub
import tensorflow as tf
import zipfile
import requests, zipfile, io
import os
import re
import argparse
import torch
from transformers import T5ForConditionalGeneration, T5Tokenizer
# pip install transformers==2.9.0
from constant import Constant
from textual_similarity import similarities, minDistance, words_distance, tags_distance, has_NNP, count_NNP
from bert_classifier import load_model, predict
const = Constant()
const.URL = "https://datascience-models-ramsri.s3.amazonaws.com/t5_paraphraser.zip"
const.MODEL_DIR = "~/Downloads/model_save1/"
def get_pretrained_model(zip_file_url):
"""
@param zip_file_url: This url references to the download link of the pre-trained model
@return: folder_path: path to store the pre-trained model
"""
model_name = zip_file_url.split("/")[-1].replace(".zip", "")
folder_path = './{}'.format(model_name)
print('Getting pretained model {}'.format(model_name))
if not os.path.exists(folder_path):
class MIPSSimulator():
'''Main class for MIPS pipeline simulator.
Provides the main method tick(), which runs pipeline
for one clock cycle.
'''
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
self.dataMemory = DataMemory(memoryFile)
self.instructionMemory = InstructionMemory(memoryFile)
self.registerFile = RegisterFile()
self.alu = ALU()
self.mainControl = MainControl()
self.splitter = Splitter()
self.signExtender = SignExtender()
self.andGate = AndGate()
self.breaker = Breaker()
self.constant4 = Constant(4)
# self.randomControl = RandomControl()
self.pcMux1 = Mux()
self.pcMux2 = Mux()
self.regMux = Mux()
self.aluMux = Mux()
self.resultMux = Mux()
self.luiMux = Mux()
self.adder = Add()
self.branchAdder = Add()
self.jumpAddress = JMPAddress()
self.shiftBranch = LeftShiftTwo()
self.shiftJump = LeftShiftTwo()
self.pc = PC(hex(0xbfc00000)) # hard coded "boot" address
self.elements = [self.constant4, self.adder, self.instructionMemory, self.breaker, self.splitter,
self.shiftJump, self.mainControl, self.regMux, self.signExtender, self.luiMux, self.registerFile,
self.jumpAddress, self.shiftBranch, self.branchAdder, self.aluMux, self.alu, self.dataMemory,
self.andGate, self.pcMux1, self.pcMux2, self.resultMux, self.registerFile, self.pc]
self._connectCPUElements()
def _connectCPUElements(self):
self.constant4.connect(
[],
['constant'],
[],
[]
)
self.adder.connect(
[(self.pc, 'pcAddress'), (self.constant4, 'constant')],
['sum'],
[],
[]
)
self.pcMux2.connect(
[(self.pcMux1, "ResultMux2"), (self.jumpAddress, "Result")],
['muxOut'],
[(self.mainControl, "JmpCtrl")],
[]
)
self.pc.connect(
[(self.pcMux2, 'muxOut')],
['pcAddress'],
[],
[]
)
self.instructionMemory.connect(
[(self.pc, "pcAddress")],
["instruction"],
[],
[]
)
self.splitter.connect(
[(self.breaker, "Instruction")],
["31-0", "25-21", "20-16", "15-11", "15-0", "25-0"],
[],
[]
)
self.mainControl.connect(
[(self.splitter, "31-0")],
[],
[],
["RegDst", "RegWrite", "ALUSrc", "ALUOp", "MemWrite", "MemtoReg", "MemRead", "ALUType", "AndGate", "JmpCtrl",
"LuiCtrl"]
)
self.regMux.connect(
[(self.splitter, "20-16"), (self.splitter, "15-11")],
["WReg"],
[(self.mainControl, "RegDst")],
[]
)
self.registerFile.connect(
[(self.splitter, "25-21"), (self.splitter, "20-16"), (self.regMux, "WReg"), (self.resultMux, "WriteData")],
["Read1", "Read2"],
[(self.mainControl, "RegWrite")],
[]
)
self.signExtender.connect(
[(self.splitter, "15-0")],
["ExtendedValue"],
[],
[]
)
self.aluMux.connect(
[(self.registerFile, "Read2"), (self.luiMux, "LuiOutput")],
["RightOp"],
[(self.mainControl, "ALUSrc")],
[]
)
self.alu.connect(
[(self.registerFile, "Read1"), (self.aluMux, "RightOp")],
["Result"],
[(self.mainControl, "ALUOp"), (self.mainControl, "ALUSrc")],
["Zero"]
)
self.dataMemory.connect(
[(self.alu, "Result"), (self.registerFile, "Read2")],
["ReadData"],
[(self.mainControl, "MemWrite"), (self.mainControl, "MemRead")],
[]
)
self.resultMux.connect(
[(self.alu, "Result"), (self.dataMemory, "ReadData")],
["WriteData"],
[(self.mainControl, "MemtoReg")],
[]
)
self.andGate.connect(
[],
[],
[(self.mainControl, "AndGate"), (self.alu, "Zero")],
["PCMuxSelect"]
)
self.shiftBranch.connect(
[(self.signExtender, "ExtendedValue")],
["ShiftedValue"],
[],
[]
)
self.branchAdder.connect(
[(self.adder, "sum"), (self.shiftBranch, "ShiftedValue")],
["branchSum"],
[],
[]
)
self.pcMux1.connect(
[(self.adder, "sum"), (self.branchAdder, "branchSum")],
["ResultMux2"],
[(self.andGate, "PCMuxSelect")],
[]
)
self.shiftJump.connect(
[(self.splitter, "25-0")],
["ShiftedValue"],
[],
[]
)
self.jumpAddress.connect(
[(self.shiftJump, "ShiftedValue"), (self.adder, "sum")],
["Result"],
[],
[]
)
self.breaker.connect(
[(self.instructionMemory, "instruction")],
["Instruction"],
[],
[]
)
self.luiMux.connect(
[(self.signExtender, "ExtendedValue"), (self.splitter, "15-0")],
["LuiOutput"],
[(self.mainControl, "LuiCtrl")],
[]
)
def clockCycles(self):
'''Returns the number of clock cycles spent executing instructions.'''
return self.nCycles
def dataMemory(self):
'''Returns dictionary, mapping memory addresses to data, holding
data memory after instructions have finished executing.'''
return self.dataMemory.memory
def registerFile(self):
'''Returns dictionary, mapping register numbers to data, holding
register file after instructions have finished executing.'''
return self.registerFile.register
#def printDataMemory(self):
#self.dataMemory.printAll()
#def printRegisterFile(self):
#self.registerFile.printAll()
def tick(self):
'''Execute one clock cycle of pipeline.'''
self.nCycles += 1
# The following is just a small sample implementation
self.pc.writeOutput()
for elem in self.elements:
elem.readControlSignals()
elem.readInput()
elem.writeOutput()
elem.setControlSignals()
self.pc.readInput()
class MIPSSimulator():
'''Main class for MIPS pipeline simulator.
Provides the main method tick(), which runs pipeline
for one clock cycle.
'''
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
self.adder = Add()
self.branchAdder = Add()
self.alu = Alu()
self.aluControl = AluControl()
self.branchNE = BranchNotEqual()
self.branch = Branch()
self.constant = Constant(4)
self.control = Control()
self.dataMemory = DataMemory(memoryFile)
self.instructionMemory = InstructionMemory(memoryFile)
self.regMux = Mux()
self.aluMux = Mux()
self.dmMux = Mux()
self.branchMux = Mux()
self.jmpMux = Mux()
self.registerFile = RegisterFile()
self.shiftLeft2 = ShiftLeft2()
self.signExtend = SignExtend()
self.jump = Jump()
self.leftShift2 = ShiftLeft2()
self.leftShift2Jump = ShiftLeft2Jump()
self.IFID = IFID()
self.IDEX = IDEX()
self.EXMEM = EXMEM()
self.MEMWB = MEMWB()
self.pc = PC(0xbfc00200) # hard coded "boot" address
self.IFIDelements = [ self.constant, self.branchMux, self.jmpMux, self.instructionMemory, self.adder ]
self.IDEXelements = [ self.control, self.registerFile, self.signExtend, self.leftShift2Jump, self.jump ]
self.EXMEMelements = [ self.regMux, self.aluControl, self.aluMux, self.alu, self.shiftLeft2, self.branchAdder, self.branchNE, self.branch ]
self.MEMWBelements = [ self.dataMemory ]
self.WBelements = [ self.dmMux ]
self.elements = [ self.IFIDelements, self.IDEXelements, self.EXMEMelements, self.WBelements]
self.pipes = [ self.IFID, self.IDEX, self.EXMEM, self.MEMWB]
self._connectCPUElements()
def _connectCPUElements(self):
###################### IFID elements ###############################
self.pc.connect(
[(self.jmpMux, 'newAddr')],
['address'],
[],
[]
)
self.constant.connect(
[],
['Constant'],
[],
[]
)
self.branchMux.connect(
[(self.adder, 'toBranchSignal'), (self.EXMEM, 'branchMuxIn')],
['branchMuxOutput'],
[(self.EXMEM, 'branchMuxControl')],
[]
)
self.jmpMux.connect(
[(self.branchMux, 'branchMuxOutput'), (self.IDEX, 'newAddr')],
['newAddr'],
[(self.IDEX, 'jump')],
[]
)
self.instructionMemory.connect(
[(self.pc, 'address')],
['op', 'rs', 'rt', 'rd', 'shamt', 'funct'],
[],
[]
)
self.adder.connect(
[(self.pc, 'address'), (self.constant, 'Constant')],
['sum'],
[],
[]
)
###################### IDEX elements ###############################
self.control.connect(
[(self.IFID, 'op')],
[],
[],
['regDst', 'aluSrc', 'memtoReg', 'regWrite', 'memRead', 'memWrite', 'branch', 'aluOp1', 'aluOp0', 'bne', 'jump']
)
self.registerFile.connect(
[(self.IFID, 'rs'), (self.IFID, 'rt'), (self.MEMWB, 'writeReg'), (self.dmMux, 'writeData')],
['rd1', 'rd2'],
[(self.MEMWB, 'regWrite')],
[]
)
self.signExtend.connect(
[(self.IFID, 'rd'), (self.IFID, 'shamt'), (self.IFID, 'funct')],
['aluMuxIn'],
[],
[]
)
self.leftShift2Jump.connect(
[(self.IFID, 'rs'), (self.IFID, 'rt'), (self.IFID, 'rd'), (self.IFID, 'shamt'), (self.IFID, 'funct')],
['jumpaddr'],
[],
[]
)
self.jump.connect(
[(self.leftShift2Jump, 'jumpaddr'), (self.IFID, 'sum')],
['newAddr'],
[],
[]
)
###################### EXMEM elements ###############################
self.regMux.connect(
[(self.IDEX, 'rt'), (self.IDEX, 'rd')],
['regMuxOutput'],
[(self.IDEX, 'regDst')],
[]
)
self.aluControl.connect(
[(self.IDEX, 'funct')],
[],
[(self.IDEX, 'aluOp1'), (self.IDEX, 'aluOp0')],
['aluOutSignal']
)
self.aluMux.connect(
[(self.IDEX, 'rd2'), (self.IDEX, 'aluMuxIn')],
['aluSecIn'],
[(self.IDEX, 'aluSrc')],
[]
)
self.alu.connect(
[(self.IDEX, 'rd1'), (self.aluMux, 'aluSecIn')],
['aluOutput'],
[(self.aluControl, 'aluOutSignal')],
['zero']
)
self.shiftLeft2.connect(
[(self.IDEX, 'aluMuxIn')],
['toAdder'],
[],
[]
)
self.branchAdder.connect(
[(self.IDEX, 'sum'), (self.shiftLeft2, 'toAdder')],
['branchMuxIn'],
[],
[]
)
self.branchNE.connect(
[],
[],
[(self.IDEX, 'bne'), (self.alu, 'zero')],
['toBranchSignal']
)
self.branch.connect(
[],
[],
[(self.IDEX, 'branch'), (self.alu, 'zero')],
['branchMuxControl']
)
###################### MEMWB elements ###############################
self.dataMemory.connect(
[(self.EXMEM, 'aluOutput'), (self.EXMEM, 'rd2')],
['toFinalMux'],
[(self.EXMEM, 'memRead'), (self.EXMEM, 'memWrite')],
[]
)
###################### WB elements ###############################
self.dmMux.connect(
[(self.MEMWB, 'aluOutput'), (self.MEMWB, 'toFinalMux')],
['writeData'],
[(self.MEMWB, 'memtoReg')],
[]
)
###################### PIPE elements ###############################
self.IFID.connect(
[(self.adder, 'sum'), (self.instructionMemory, 'op'),
(self.instructionMemory, 'rs'), (self.instructionMemory, 'rt'),
(self.instructionMemory, 'rd'), (self.instructionMemory, 'shamt'),
(self.instructionMemory, 'funct')],
['sum', 'op', 'rs', 'rt', 'rd', 'shamt', 'funct'],
[],
[]
)
self.IDEX.connect(
[(self.IFID, 'sum'), (self.IFID, 'op'), (self.IFID, 'rt'),
(self.IFID, 'rd'), (self.IFID, 'shamt'), (self.IFID, 'funct'),
(self.registerFile, 'rd1'), (self.registerFile, 'rd2'), (self.signExtend, 'aluMuxIn'),
(self.jump, 'newAddr') ],
['sum', 'op', 'rt', 'rd', 'shamt', 'funct', 'rd1', 'rd2', 'aluMuxIn', 'newAddr' ],
[(self.control, 'regDst'), (self.control, 'aluSrc'), (self.control, 'memtoReg'), (self.control, 'regWrite'),
(self.control, 'memRead'), (self.control, 'memWrite'), (self.control, 'branch'),
(self.control, 'aluOp1'), (self.control, 'aluOp0'), (self.control, 'bne'), (self.control, 'jump')],
['regDst', 'aluSrc', 'memtoReg', 'regWrite', 'memRead', 'memWrite', 'branch', 'aluOp1', 'aluOp0', 'bne', 'jump']
)
self.EXMEM.connect(
[(self.IDEX, 'rd2'), (self.alu, 'aluOutput'), (self.regMux, 'writeReg'), (self.branchAdder, 'branchMuxIn')],
['rd2', 'aluOutput', 'writeReg', 'branchMuxIn'],
[(self.IDEX, 'memtoReg'), (self.IDEX, 'memtoRead'), (self.IDEX, 'memWrite'), (self.branch ,'branchMuxControl'), (self.IDEX, 'regWrite')],
['memtoReg', 'memtoRead', 'memWrite', 'branchMuxControl', 'regWrite']
)
self.MEMWB.connect(
[(self.EXMEM, 'writeReg'), (self.EXMEM, 'aluOutput'), (self.EXMEM, 'toFinalMux')],
['writeReg', 'aluOutput', 'toFinalMux'],
[(self.EXMEM, 'memtoReg'), (self.EXMEM, 'regWrite')],
['memtoReg', 'regWrite']
)
def clockCycles(self):
'''Returns the number of clock cycles spent executing instructions.'''
return self.nCycles
def dataMemory(self):
'''Returns dictionary, mapping memory addresses to data, holding
data memory after instructions have finished executing.'''
return self.dataMemory.memory
def registerFile(self):
'''Returns dictionary, mapping register numbers to data, holding
register file after instructions have finished executing.'''
return self.registerFile.register
def printDataMemory(self):
self.dataMemory.printAll()
def printRegisterFile(self):
self.registerFile.printAll()
def tick(self):
'''Execute one clock cycle of pipeline.'''
self.nCycles += 1
# The following is just a small sample implementation
self.pc.writeOutput()
for elem in self.elements:
for e in elem:
e.readControlSignals()
e.readInput()
e.writeOutput()
e.setControlSignals()
self.pc.readInput()
class MIPSSimulator():
'''Main class for MIPS pipeline simulator.
Provides the main method tick(), which runs pipeline
for one clock cycle.
'''
def __init__(self, memoryFile):
self.nCycles = 0 # Used to hold number of clock cycles spent executing instructions
# Fetch
self.PCMux = Mux()
self.ProgramC = PC(long(0xbfc00200))
self.InstMem = InstructionMemory(memoryFile)
self.IFadder = Add()
self.JMux = Mux()
self.IFaddconst = Constant(4)
self.IF_ID_Wall = Wall()
self.fetchgroup = {}
# Decode
self.register = RegisterFile()
self.signext = SignExtender()
self.control = ControlElement()
self.jmpCalc = JumpCalc()
self.ID_EX_Wall = Wall()
# Execute
self.EXadder = Add()
self.shiftL = LeftShifter()
self.ALogicUnit = ALU()
self.ALUSrcMux = Mux()
self.RegDstMux = Mux()
self.ALUctrl = AluControl()
self.EX_MEM_Wall= Wall()
# Memory
self.storage = DataMemory(memoryFile)
self.brnch = Branch()
self.MEM_WB_Wall= Wall()
# Write Back
self.WBmux = Mux()
self.ProgramC
self.elements1 = [self.InstMem, self.IFaddconst, self.IFadder, self.PCMux, self.JMux]
self.elements2 = [self.control, self.register, self.signext, self.jmpCalc]
self.elements3 = [self.shiftL, self.ALUSrcMux, self.RegDstMux, self.ALUctrl, self.ALogicUnit, self.EXadder]
self.elements4 = [self.brnch, self.storage]
self.elementsboot = [self.IFaddconst, self.IFadder, self.InstMem,
self.IF_ID_Wall, self.register, self.signext, self.control, self.jmpCalc,
self.ID_EX_Wall, self.RegDstMux, self.shiftL, self.EXadder, self.ALUSrcMux, self.ALUctrl, self.ALogicUnit,
self.EX_MEM_Wall, self.brnch, self.storage,
self.MEM_WB_Wall, self.WBmux, self.PCMux, self.JMux]
self.walls = [self.MEM_WB_Wall, self.EX_MEM_Wall, self.ID_EX_Wall, self.IF_ID_Wall]
self._connectCPUElements()
def _connectCPUElements(self):
# IF
self.PCMux.connect(
[(self.IFadder, "adderout"), (self.EX_MEM_Wall, "adderoutput")],
["PCmuxoutput"],
[(self.brnch, "PCSrc")],
[]
)
self.JMux.connect(
[(self.PCMux, "PCmuxoutput"), (self.jmpCalc, "output")],
["output"],
[(self.control, "Jump")],
[]
)
self.IFaddconst.connect(
[],
['constant'],
[],
[]
)
self.ProgramC.connect(
[(self.JMux, "output")],
["output"],
[],
[]
)
self.InstMem.connect(
[(self.ProgramC, "output")],
["opcode", "rs", "rt", "rd", "shamt", "funct", "imm", "addr"],
[],
[]
)
self.IFadder.connect(
[(self.ProgramC, "output"), (self.IFaddconst, "constant")],
["adderout"],
[],
[]
)
self.IF_ID_Wall.connect(
[(self.InstMem, "opcode"),(self.InstMem, "rs"),
(self.InstMem, "rt"),(self.InstMem, "rd"),
(self.InstMem, "shamt"), (self.InstMem, "funct"),
(self.InstMem, "imm"), (self.InstMem, "addr"),
(self.IFadder, "adderout")],
["opcode", "rs", "rt", "rd",
"shamt", "funct", "imm", "addr",
"adderout"],
[],
[]
)
# IF
# ID
self.register.connect(
[(self.IF_ID_Wall, "rs"), (self.IF_ID_Wall, "rt"),
(self.MEM_WB_Wall, "regdstoutput"), (self.WBmux, "output")],
["Reg1", "Reg2"],
[(self.MEM_WB_Wall, "RegWrite")],
[]
)
self.signext.connect(
[(self.IF_ID_Wall, "imm")],
["extended"],
[],
[]
)
self.control.connect(
[(self.IF_ID_Wall, "opcode")],
[],
[],
["RegDst", "RegWrite", "ALUSrc", "MemtoReg",
"MemWrite", "MemRead", "Branch", "ALUOp", "Jump"]
)
self.jmpCalc.connect(
[(self.IF_ID_Wall, "addr"), (self.IF_ID_Wall, "adderout")],
["output"],
[],
[]
)
self.ID_EX_Wall.connect(
[(self.register, "Reg1"), (self.register, "Reg2"),
(self.signext, "extended"), (self.jmpCalc, "output"),
(self.IF_ID_Wall, "adderout"), (self.IF_ID_Wall, "funct"),
(self.IF_ID_Wall, "rd"), (self.IF_ID_Wall, "addr"),
(self.IF_ID_Wall, "rt")],
["Reg1", "Reg2", "extended", "output",
"adderout", "funct", "rd", "addr", "rt"],
[(self.control, "RegDst"), (self.control, "RegWrite"),
(self.control, "ALUSrc"), (self.control, "MemtoReg"),
(self.control, "MemWrite"), (self.control, "MemRead"),
(self.control, "Branch"), (self.control, "ALUOp"),
(self.control, "Jump")],
["RegDst", "RegWrite", "ALUSrc", "MemtoReg",
"MemWrite", "MemRead", "Branch", "ALUOp", "Jump"]
)
#ID
#EX
self.EXadder.connect(
[(self.ID_EX_Wall, "adderout"), (self.shiftL, "shifted")],
["output"],
[],
[]
)
self.shiftL.connect(
[(self.ID_EX_Wall, "extended")],
["shifted"],
[],
[]
)
self.ALogicUnit.connect(
[(self.ID_EX_Wall, "Reg1"), (self.ALUSrcMux, "output")],
["result"],
[(self.ALUctrl, "ALUctrlsig")],
["zero"]
)
self.ALUSrcMux.connect(
[(self.ID_EX_Wall, "Reg2"), (self.ID_EX_Wall, "extended")],
["output"],
[(self.ID_EX_Wall, "ALUSrc")],
[]
)
self.RegDstMux.connect(
[(self.ID_EX_Wall, "rt"), (self.ID_EX_Wall, "rd")],
["RegDstoutput"],
[(self.ID_EX_Wall, "RegDst")],
[]
)
self.ALUctrl.connect(
[(self.ID_EX_Wall, "funct")],
[],
[(self.ID_EX_Wall, "ALUOp")],
["ALUctrlsig"]
)
self.EX_MEM_Wall.connect(
[(self.EXadder, "output"), (self.ALogicUnit, "result"),
(self.ID_EX_Wall, "rt"), (self.RegDstMux, "RegDstoutput")],
["adderoutput", "result", "rt", "regdstoutput"],
[(self.ID_EX_Wall, "RegWrite"), (self.ID_EX_Wall, "MemtoReg"),
(self.ID_EX_Wall, "MemWrite"), (self.ID_EX_Wall, "MemRead"),
(self.ID_EX_Wall, "Branch"), (self.ALogicUnit, "zero")],
["RegWrite", "MemtoReg", "MemWrite", "MemRead", "Branch", "zero"]
)
#EX
#MEM
self.storage.connect(
[(self.EX_MEM_Wall, "result"), (self.EX_MEM_Wall, "rt")],
["data"],
[(self.EX_MEM_Wall, "MemWrite"), (self.EX_MEM_Wall, "MemRead")],
[]
)
self.brnch.connect(
[],
[],
[(self.EX_MEM_Wall, "Branch"), (self.EX_MEM_Wall, "zero")],
["PCSrc"]
)
self.MEM_WB_Wall.connect(
[(self.EX_MEM_Wall, "adderoutput"), (self.storage, "data"),
(self.EX_MEM_Wall, "regdstoutput")],
["adderoutput", "data", "regdstoutput"],
[(self.EX_MEM_Wall, "RegWrite"), (self.EX_MEM_Wall, "MemtoReg")],
["RegWrite", "MemtoReg"]
)
#MEM
#WB
self.WBmux.connect(
[(self.MEM_WB_Wall, "adderoutput"), (self.MEM_WB_Wall, "data")],
["output"],
[(self.MEM_WB_Wall, "MemtoReg")],
[]
)
def clockCycles(self):
'''Returns the number of clock cycles spent executing instructions.'''
return self.nCycles
def dataMemory(self):
'''Returns dictionary, mapping memory addresses to data, holding
data memory after instructions have finished executing.'''
return self.dataMemory.memory
def registerFile(self):
'''Returns dictionary, mapping register numbers to data, holding
register file after instructions have finished executing.'''
return self.registerFile.register
def printDataMemory(self):
self.dataMemory.printAll()
def printRegisterFile(self):
self.registerFile.printAll()
def bootup(self):
self.ProgramC.writeOutput()
for elem in self.elementsboot:
elem.readControlSignals()
elem.readInput()
elem.writeOutput()
elem.setControlSignals()
self.ProgramC.readInput()
def tick(self):
'''Execute one clock cycle of pipeline.'''
self.nCycles += 1
self.ProgramC.writeOutput()
for elem in self.walls:
elem.writeOutput()
elem.setControlSignals()
self.WBmux.readControlSignals()
self.WBmux.readInput()
self.WBmux.writeOutput()
self.WBmux.setControlSignals()
for elem in self.elements4:
elem.readControlSignals()
elem.readInput()
elem.writeOutput()
elem.setControlSignals()
for elem in self.elements3:
elem.readControlSignals()
elem.readInput()
elem.writeOutput()
elem.setControlSignals()
for elem in self.elements2:
elem.readControlSignals()
elem.readInput()
elem.writeOutput()
elem.setControlSignals()
for elem in self.elements1:
elem.readControlSignals()
elem.readInput()
elem.writeOutput()
elem.setControlSignals()
for elem in self.walls:
elem.readControlSignals()
elem.readInput()
self.register.printAll()
self.ProgramC.readInput()
print "number of cycles", self.nCycles, "\n"
import argparse
import os
import tensorflow as tf
tf.compat.v1.enable_eager_execution()
from paraphrase_questions import paraphrase_questions, get_pretrained_model, prepare_model, set_seed, pick_final_sentence, pick_final_sentence_advanced
from constant import Constant
const = Constant()
seperator = "\t"
const.URL = "https://datascience-models-ramsri.s3.amazonaws.com/t5_paraphraser.zip"
def batch_paraphrase(templates_path, model_dir):
folder_path = get_pretrained_model(const.URL)
set_seed(42)
tokenizer, device, model = prepare_model(folder_path)
dir = os.path.realpath(templates_path)
with open(dir, "r") as lines:
with open(dir + "_paraphrased", "w") as w:
for line in lines:
prop = line.strip("\n").split(seperator)
question = prop[3]
paraphrased_candidates = paraphrase_questions(
tokenizer, device, model, question)
paraphrased = pick_final_sentence(question,
paraphrased_candidates)
advanced = pick_final_sentence_advanced(
device, question, paraphrased_candidates, model_dir)
w.write(line)
print("Original", line)
def __init__(self):
self.log = Logging()
self.constant = Constant()
self.maps = {} # ID(int), MAP(object)