('r7', 32),
('r8', 32),
('r9', 32),
('sl', 32),
('fp', 32),
('ip', 32),
('sp', 32),
('lr', 32),
('pc', 32),
('cpsr', 32),
# FIXME shadow regs go here (but are not encoded in
# instructions... they are used by context only)
)
l = locals()
e_reg.addLocalEnums(l, arm_regs)
PSR_N = 31 # negative
PSR_Z = 30 # zero
PSR_C = 29 # carry
PSR_V = 28 # oVerflow
PSR_Q = 27
PSR_J = 24
PSR_GE = 16
PSR_E = 9
PSR_A = 8
PSR_I = 7
PSR_F = 6
PSR_T = 5
PSR_M = 0
reg_data.append((arm_regs[ridx][0]+"_"+msname, 32))
reg_table[ridx+offset] = idx
#print idx
# PC
reg_table[PSR_offset-2] = 15
# CPSR
reg_table[PSR_offset-1] = 16
# PSR
reg_table[PSR_offset] = len(reg_data)
reg_data.append(("SPSR_"+msname, 32))
# done with banked register translation table
l = locals()
e_reg.addLocalEnums(l, arm_regs)
PSR_N = 31 # negative
PSR_Z = 30 # zero
PSR_C = 29 # carry
PSR_V = 28 # oVerflow
PSR_Q = 27
PSR_IT = 25
PSR_J = 24
PSR_DNM = 20
PSR_GE = 16
PSR_E = 9
PSR_A = 8
PSR_I = 7
PSR_F = 6
PSR_T = 5
# Extended Control registers (REX.R)
("ctrl8",64),("ctrl9",64),("ctrl10",64),("ctrl11",64),("ctrl12",64),("ctrl13",64),("ctrl14",64),("ctrl15",64),
# Test registers
("test0", 32),("test1", 32),("test2", 32),("test3", 32),("test4", 32),("test5", 32),("test6", 32),("test7", 32),
# Segment registers
("es", 16),("cs",16),("ss",16),("ds",16),("fs",16),("gs",16),
# FPU Registers
("st0", 128),("st1", 128),("st2", 128),("st3", 128),("st4", 128),("st5", 128),("st6", 128),("st7", 128),
# Leftovers ;)
("eflags", 32), ("rip", 64),
]
# Build up a set of accessable constants
l = locals()
e_reg.addLocalEnums(l, amd64regs)
amd64meta = e_i386.i386meta + [
("eax", REG_RAX, 0, 32),
("ecx", REG_RCX, 0, 32),
("edx", REG_RDX, 0, 32),
("ebx", REG_RBX, 0, 32),
("esp", REG_RSP, 0, 32),
("ebp", REG_RBP, 0, 32),
("esi", REG_RSI, 0, 32),
("edi", REG_RDI, 0, 32),
("ax", REG_RAX, 0, 16),
("cx", REG_RCX, 0, 16),
("dx", REG_RDX, 0, 16),
("bx", REG_RBX, 0, 16),
("eip", 32),
]
def getRegOffset(regs, regname):
# NOTE: dynamically calculate this on import so we are less
# likely to f**k it up...
for i, (name, width) in enumerate(regs):
if name == regname:
return i
raise Exception("getRegOffset doesn't know about: %s" % regname)
# Setup REG_EAX and the like in our module
l = locals()
e_reg.addLocalEnums(l, i386regs)
i386meta = [
("ax", REG_EAX, 0, 16),
("cx", REG_ECX, 0, 16),
("dx", REG_EDX, 0, 16),
("bx", REG_EBX, 0, 16),
("sp", REG_ESP, 0, 16),
("bp", REG_EBP, 0, 16),
("si", REG_ESI, 0, 16),
("di", REG_EDI, 0, 16),
("al", REG_EAX, 0, 8),
("cl", REG_ECX, 0, 8),
("dl", REG_EDX, 0, 8),
("bl", REG_EBX, 0, 8),
("ah", REG_EAX, 8, 8),
("eip", 32),
]
def getRegOffset(regs, regname):
# NOTE: dynamically calculate this on import so we are less
# likely to f**k it up...
for i, (name, width) in enumerate(regs):
if name == regname:
return i
raise Exception("getRegOffset doesn't know about: %s" % regname)
# dynamically create REG_EAX and the like in our module
l = locals()
e_reg.addLocalEnums(l, i386regs)
i386meta = [
("ax", REG_EAX, 0, 16),
("cx", REG_ECX, 0, 16),
("dx", REG_EDX, 0, 16),
("bx", REG_EBX, 0, 16),
("sp", REG_ESP, 0, 16),
("bp", REG_EBP, 0, 16),
("si", REG_ESI, 0, 16),
("di", REG_EDI, 0, 16),
("al", REG_EAX, 0, 8),
("cl", REG_ECX, 0, 8),
("dl", REG_EDX, 0, 8),
("bl", REG_EBX, 0, 8),
("ah", REG_EAX, 8, 8),
("st0", 128),
("st1", 128),
("st2", 128),
("st3", 128),
("st4", 128),
("st5", 128),
("st6", 128),
("st7", 128),
# Leftovers ;)
("eflags", 32),
("rip", 64),
]
# Build up a set of accessable constants
l = locals()
e_reg.addLocalEnums(l, amd64regs)
amd64meta = e_i386.i386meta + [
("eax", REG_RAX, 0, 32),
("ecx", REG_RCX, 0, 32),
("edx", REG_RDX, 0, 32),
("ebx", REG_RBX, 0, 32),
("esp", REG_RSP, 0, 32),
("ebp", REG_RBP, 0, 32),
("esi", REG_RSI, 0, 32),
("edi", REG_RDI, 0, 32),
("ax", REG_RAX, 0, 16),
("cx", REG_RCX, 0, 16),
("dx", REG_RDX, 0, 16),
("bx", REG_RBX, 0, 16),
("sp", REG_RSP, 0, 16),
('er0', 32),
('er1', 32),
('er2', 32),
('er3', 32),
('er4', 32),
('er5', 32),
('er6', 32),
('sp', 32),
('pc', 24),
('ccr', 8),
('exr', 8),
)
l = locals()
e_reg.addLocalEnums(l, h8_regs)
REG_CCR_T = 7
REG_CCR_U1= 6
REG_CCR_H = 5
REG_CCR_U0= 4
REG_CCR_N = 3
REG_CCR_Z = 2
REG_CCR_V = 1
REG_CCR_C = 0
ccr_fields = [None for x in range(8)]
for k,v in list(locals().items()):
if k.startswith('REG_CCR_'):
ccr_fields[v] = k
GeneralRegGroup = ('general', priregisters, )
metaregs = [ (registers[x], x, 0, 16) for x in range(len(registers)) ]
statmetas = [
('C', REG_SR, 0, 1, 'Carry Flag'),
('Z', REG_SR, 1, 1, 'Zero Flag'),
('N', REG_SR, 2, 1, 'Negative (Sign) Flag'),
('GIE', REG_SR, 3, 1, 'General Interrupt Enable Flag'),
('CPUOFF', REG_SR, 4, 1, 'CPU Off Flag'),
('OSCOFF', REG_SR, 5, 1, 'Oscillator Off Flag'),
('SCG0', REG_SR, 6, 1, 'System Clock Generator 0 Off Flag'),
('SCG1', REG_SR, 7, 1, 'System Clock Generotor 1 Off Flag'),
('V', REG_SR, 8, 1, 'Overflow Flag'),
]
l = locals()
e_reg.addLocalEnums(l, reginfo)
e_reg.addLocalStatusMetas(l, priregisters, statmetas, 'SR')
#e_reg.addLocalMetas(l, i386meta)
class Msp430RegisterContext(e_reg.RegisterContext):
def __init__(self):
e_reg.RegisterContext.__init__(self)
self.loadRegDef(reginfo)
self.loadRegMetas(metaregs, statmetas=statmetas)
self.setRegisterIndexes(REG_PC, REG_SP, srindex=REG_SR)
priregisters,
)
metaregs = [(registers[x], x, 0, 16) for x in range(len(registers))]
statmetas = [
('C', REG_SR, 0, 1, 'Carry Flag'),
('Z', REG_SR, 1, 1, 'Zero Flag'),
('N', REG_SR, 2, 1, 'Negative (Sign) Flag'),
('GIE', REG_SR, 3, 1, 'General Interrupt Enable Flag'),
('CPUOFF', REG_SR, 4, 1, 'CPU Off Flag'),
('OSCOFF', REG_SR, 5, 1, 'Oscillator Off Flag'),
('SCG0', REG_SR, 6, 1, 'System Clock Generator 0 Off Flag'),
('SCG1', REG_SR, 7, 1, 'System Clock Generotor 1 Off Flag'),
('V', REG_SR, 8, 1, 'Overflow Flag'),
]
l = locals()
e_reg.addLocalEnums(l, reginfo)
e_reg.addLocalStatusMetas(l, priregisters, statmetas, 'SR')
#e_reg.addLocalMetas(l, i386meta)
class Msp430RegisterContext(e_reg.RegisterContext):
def __init__(self):
e_reg.RegisterContext.__init__(self)
self.loadRegDef(reginfo)
self.loadRegMetas(metaregs, statmetas=statmetas)
self.setRegisterIndexes(REG_PC, REG_SP, srindex=REG_SR)
z80regs = [
('AF', 16),
('BC', 16),
('DE', 16),
('HL', 16),
('IX', 16),
('IY', 16),
('PC', 16),
('SP', 16),
('I', 8),
('R', 8),
]
l = locals()
e_reg.addLocalEnums(l, z80regs)
z80meta = [
('A', REG_AF, 8, 8),
('B', REG_BC, 8, 8),
('C', REG_BC, 0, 8),
('D', REG_DE, 8, 8),
('E', REG_DE, 0, 8),
('F', REG_AF, 0, 8),
('H', REG_HL, 8, 8),
('L', REG_HL, 0, 8),
]
e_reg.addLocalMetas(l, z80meta)
import envi.registers as e_reg
from envi.archs.msp430.const import *
registers = [
'pc','sp','sr','cg','r4','r5','r6','r7',
'r8','r9','r10','r11','r12','r13','r14','r15'
]
registers_info = [ (reg, 16) for reg in registers ]
l = locals()
e_reg.addLocalEnums(l, registers_info)
registers_meta = [
("r0", REG_PC, 0, 16),
("r1", REG_SP, 0, 16),
("r2", REG_SR, 0, 16),
("r3", REG_CG, 0, 16),
]
status_meta = [
('C', REG_SR, 0, 1, 'Carry Flag'),
('Z', REG_SR, 1, 1, 'Zero Flag'),
('N', REG_SR, 2, 1, 'Negative (Sign) Flag'),
('GIE', REG_SR, 3, 1, 'General Interrupt Enable Flag'),
('CPUOFF', REG_SR, 4, 1, 'CPU Off Flag'),
('OSCOFF', REG_SR, 5, 1, 'Oscillator Off Flag'),
('SCG0', REG_SR, 6, 1, 'System Clock Generator 0 Off Flag'),
('SCG1', REG_SR, 7, 1, 'System Clock Generotor 1 Off Flag'),
('V', REG_SR, 8, 1, 'Overflow Flag'),
z80regs = [
("AF", 16),
("BC", 16),
("DE", 16),
("HL", 16),
("IX", 16),
("IY", 16),
("PC", 16),
("SP", 16),
("I", 8),
("R", 8),
]
l = locals()
e_reg.addLocalEnums(l, z80regs)
z80meta = [
("A", REG_AF, 8, 8),
("B", REG_BC, 8, 8),
("C", REG_BC, 0, 8),
("D", REG_DE, 8, 8),
("E", REG_DE, 0, 8),
("F", REG_AF, 0, 8),
("H", REG_HL, 8, 8),
("L", REG_HL, 0, 8),
]
e_reg.addLocalMetas(l, z80meta)