def __init__(self, platform, **kwargs): clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() self.submodules.oled = oled.OLED(platform.request("oled")) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True))
def __init__(self, platform, **kwargs): clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, cpu_type=None, l2_size=32, with_uart=False, with_timer=False) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # uart self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone)
def __init__(self, platform, **kwargs): clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="NeTV2 LiteX Base SoC", **kwargs) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # sdram bist generator_port = self.sdram.crossbar.get_port(mode="write") self.submodules.generator = LiteDRAMBISTGenerator(generator_port) checker_port = self.sdram.crossbar.get_port(mode="read") self.submodules.checker = LiteDRAMBISTChecker(checker_port)
def __init__(self, platform, target_name): self.submodules.dna = dna.DNA() self.submodules.git = git.GitInfo() target = target_name.lower()[:-3] self.submodules.platform = platform_info.PlatformInfo( platform.name, target) if "xc7" in platform.device: self.submodules.xadc = xadc.XADC()
def __init__(self, platform, **kwargs): kwargs['cpu_type'] = None clk_freq = 100 * 1000000 SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, ident="NeTV2 LiteX Base SoC", with_uart=False, **kwargs) self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), self.clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("A7DDRPHY_BITSLIP", 2) self.add_constant("A7DDRPHY_DELAY", 8) sdram_module = MT41J128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # sdram bist ddr_generator_port = self.sdram.crossbar.get_port(mode="write") self.submodules.ddr_generator = LiteDRAMBISTGenerator( ddr_generator_port) ddr_checker_port = self.sdram.crossbar.get_port(mode="read") self.submodules.ddr_checker = LiteDRAMBISTChecker(ddr_checker_port) # led blink counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, platform, with_uart_bridge=True, **kwargs): clk_freq = 125*1000000 kwargs['cpu_type'] = None SoCCore.__init__(self, platform, clk_freq, shadow_base=0x00000000, csr_data_width=32, with_uart=False, ident="NeTV2 LiteX PCIe SoC", with_timer=False, **kwargs) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=1) # pci endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.add_cpu_or_bridge(LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)) self.add_wb_master(self.cpu_or_bridge.wishbone) # pcie dma self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) if with_uart_bridge: self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # pcie msi self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.interrupt) self.interrupts = { "dma_writer": self.dma.writer.irq, "dma_reader": self.dma.reader.irq } for k, v in sorted(self.interrupts.items()): self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v) # flash the led on pcie clock counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, platform, with_sdram_bist=True, bist_async=True, bist_random=False): clk_freq = 100*1000000 SoCSDRAM.__init__(self, platform, clk_freq, cpu_type=None, l2_size=32, csr_data_width=32, with_uart=False, with_timer=False) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # sdram bist if with_sdram_bist: generator_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys") self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random) checker_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys") self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random) # uart self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) # logic analyzer analyzer_signals = [Signal(2)] if False: analyzer_signals = [ generator_user_port.cmd.valid, generator_user_port.cmd.ready, generator_user_port.cmd.we, generator_user_port.cmd.adr, generator_user_port.wdata.valid, generator_user_port.wdata.ready, generator_user_port.wdata.we, self.generator.start.re, self.checker.start.re ] if False: gen_data = Signal(32) read_data = Signal(32) self.comb += [ gen_data.eq(self.checker.core.gen.o), read_data.eq(checker_user_port.rdata.data) ] analyzer_signals = [ checker_user_port.cmd.valid, checker_user_port.cmd.ready, checker_user_port.cmd.we, checker_user_port.cmd.adr, checker_user_port.rdata.valid, checker_user_port.rdata.ready, self.generator.start.re, self.checker.start.re, gen_data, read_data, self.checker.core.errors ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, platform, platform_name, target_name): self.submodules.dna = dna.DNA() self.submodules.git = git.GitInfo() self.submodules.platform = platform_info.PlatformInfo( platform_name, target_name)